Steffen Buch

Low power synthesizable register files for processor and IP cores

In this paper, low power architectures of register files on register-transfer level (RTL) are presented. The proposed architectures are implemented using a standard hardware description language (HDL) and can be synthesized within a commercial semi-custom design flow. The presented register file architectures are ideally suited for synthesizable processor cores or IP blocks. It is shown, that significant power savings of register files can be achieved, if a clock gating scheme for register files different from the one usually applied is used. As an alternative, an architecture with register isolation is presented. The third proposed register file architecture is based on interleaving known from signal processing implementations. Although, interleaving is usually applied to multichannel algorithms, it is shown that this architecture can also be applied to certain single channel cases. Experimental results of all three register file architectures prove that a significant power reduction can be achieved.

An instruction set for the efficient implementation of the CORDIC algorithm

In this paper, an instruction set for a processor is proposed which is very well suited for the implementation of the CORDIC algorithm. This instruction set is efficient for both the hardware implementation of the processor and the CORDIC software implementation. This is achieved by conditional instructions which reduce the number of lines of code significantly. In order to implement the conditional instructions in the processor hardware model with a conventional ALU, only a few additional gates are necessary. Thus, the increase in area and timing of the processor is negligible due to these additional instructions. The presented approach is a very good trade-off from a hardware/software co-design perspective if both the hardware and software efficiency is important.