Sven Simon

The impact of clock gating schemes on the power dissipation of synthesizable register files

In this paper, the power dissipation of synthesizable register files with respect to different clock gating schemes is examined. Clock gating is a well-known technique for power reduction of sequential circuits. Although different clock gating schemes exist, there is no fundamental difference in the power dissipation of sequential logic because the data input signals of disabled flip-flops do not change when the clock signal is disabled. However, it is shown here that in contrast to sequential logic the clock gating scheme has significant impact on the power dissipation of register files due to signal changes of the data input port. The major result of this work is that the power dissipation of register files can be reduced significantly, if a clock gating scheme different from that one usually recommended for sequential logic is applied.

Low power synthesizable register files for processor and IP cores

In this paper, low power architectures of register files on register-transfer level (RTL) are presented. The proposed architectures are implemented using a standard hardware description language (HDL) and can be synthesized within a commercial semi-custom design flow. The presented register file architectures are ideally suited for synthesizable processor cores or IP blocks. It is shown, that significant power savings of register files can be achieved, if a clock gating scheme for register files different from the one usually applied is used. As an alternative, an architecture with register isolation is presented. The third proposed register file architecture is based on interleaving known from signal processing implementations. Although, interleaving is usually applied to multichannel algorithms, it is shown that this architecture can also be applied to certain single channel cases. Experimental results of all three register file architectures prove that a significant power reduction can be achieved.

Low power register file architecture for application specific DSPs

In this paper, an architecture for register files suited for synthesizable DSP cores is proposed. The principal focus is on the implementation of DSP algorithms with several identical channels, used in e.g. stereo audio, filter banks or network IC implementations. Nevertheless, it is shown that the result of this work can be extended to many single channel applications by formal assignment of operations to several channels. The new register file architecture is especially suited for a standard semi-custom design flow based on common hardware description languages in conjunction with commercial synthesis tools. The level of abstraction used here is the register-transfer level (RTL). Due to the proposed register file architecture, the power dissipation of our application is reduced by 30% compared to the conventional implementation.

Static timing analysis with rigorous exploitation of setup time margins

In this paper, a reasoning for static timing analysis with rigorous exploitation of the setup time margins is derived. This approach enables a more precise reasoning of the maximal operating frequency of high throughput standard cell designs. Besides a framework for calculations the experimental results for a typical high speed building block are presented. This technique can be applied in alliance with statistical timing approaches leading to gains in performance in the region of one technology migration step.

A power dissipation comparison of ALU-architectures for ASIPs

This paper focuses on the implementation of different ALU architectures for ASIPs with greater emphasis on the reduction of power dissipation. The examinations are based on a workframe for the design of fully configurable ASIP with proper selection of power efficient ALU architectures for the implementation of digital filters. Architectures with high ALU complexity and low ALU access rate are compared against architectures with low ALU complexity and high ALU access rate to find out the one that provides a better power efficiency. More in detail, we discuss the reduction of the power dissipation by choosing optimized ALU architectures for the implementation of digital filters.

A power efficient register file architecture using master latch sharing

This paper introduces a method of reducing area and power consumption of a synthesizable register file by using a single master latch shared by a number of slaves. It investigates potential timing problems and discusses possible solutions. Presented simulation results show that, depending on the size of the register file, reduction of power consumption of more than 50% is achievable.

Power reduction of ASIPs by distributing the workload on several ASIP-instances

In modern SoC designs, more and more application specific instruction-set processors (ASIPs) are used. They enable a trade off between the flexibility due to the software implementation of algorithms and hardware efficiency arising from the ASIP architecture which is optimized with respect to the application. In this paper, it is shown that the total power dissipation could be reduced by distributing the software tasks on several identical ASIP instances although the throughput of a single ASIP would be sufficient for all tasks. In addition, it is shown that for power comparisons of processor instances, the number of executed lines of code is a parameter which gives more insight into power comparisons than the clock rate.

Register Isolation for Synthesizable Register Files

In this paper, a low power synthesizable register file architecture is presented. The register file is modeled on register-transfer level (RTL). It is suitable for technology independent IP-core and processor models. The data inputs of all registers of the register file are connected to a data bus. Similar to operand isolation for combinational logic blocks we use blocking logic in order to isolate registers from transitions on the data bus. The registers are divided into groups and blocking logic is inserted for each group. Even if no spurious transitions occur on the data bus, the power dissipation of the register file can be reduced applying this register file architecture.

An instruction set for the efficient implementation of the CORDIC algorithm

In this paper, an instruction set for a processor is proposed which is very well suited for the implementation of the CORDIC algorithm. This instruction set is efficient for both the hardware implementation of the processor and the CORDIC software implementation. This is achieved by conditional instructions which reduce the number of lines of code significantly. In order to implement the conditional instructions in the processor hardware model with a conventional ALU, only a few additional gates are necessary. Thus, the increase in area and timing of the processor is negligible due to these additional instructions. The presented approach is a very good trade-off from a hardware/software co-design perspective if both the hardware and software efficiency is important.

A high-speed transceiver architecture implementable as synthesizable IP core

In this work, a synthesizable architecture for serial high speed transceiver is presented, which can be implemented on register-transfer level (RTL) with standard hardware description languages (HDL). The proposed implementation as a soft IP macro can be synthesized applying a semi-custom design flow, widely used in industry whenever possible. Generally, the implementation of high speed transceivers is a typical domain of a full custom design style because the timing critical parts are realized by dedicated transistor level design of the PLL/DLL based architectures. Compared to this method, the design productivity can be enhanced significantly, with the usage of this soft IP macro. With the presented implementation, data rates of about 1 GBit/s can be achieved. This is certainly less compared to full custom implementations. Nevertheless, this is an appealing solution for short design time and low cost design, if the achieved data rate is sufficient. In addition, current research show that data rates above the mentioned result can be achieved.