Stephan Eggersgluss

On Acceleration of SAT-Based ATPG for Industrial Designs

Due to the rapidly growing size of integrated circuits, there is a need for new algorithms for automatic test pattern generation (ATPG). While classical algorithms reach their limit, there have been recent advances in algorithms to solve Boolean Satisfiability (SAT). Because Boolean SAT solvers are working on conjunctive normal forms (CNFs), the problem has to be transformed. During transformation, relevant information about the problem might get lost and, therefore, is not available in the solving process. In this paper, we present a technique that applies structural knowledge about the circuit during the transformation. As a result, the size of the problem instances decreases, as well as the run time of the ATPG process. The technique was implemented, and experimental results are presented. The approach was combined with the ATPG framework of NXP Semiconductors. It is shown that the overall performance of an industrial framework can significantly be improved. Further experiments show the benefits with regard to the efficiency and robustness of the combined approach.

Improved SAT-based ATPG: more constraints, better compaction

Automatic Test Pattern Generation (ATPG) based on Boolean Satisfiability (SAT) is a robust alternative to classical structural ATPG. Due to the powerful reasoning engines of modern SAT solvers, SAT-based algorithms typically provide a high test coverage because of the ability to reliably classify hard-to-detect faults. However, a drawback of SAT-based ATPG is the test compaction ability. In this paper, we propose an enhanced dynamic test compaction approach which leverages the high implicative power of modern SAT solvers. Fault detection constraints are encoded into the SAT instance and a formal optimization procedure is applied to increase the detection ability of the generated tests. Experiments show that the proposed approach is able to achieve high compaction - for certain benchmarks even smaller test sets than the currently best known results are obtained.

SWORD: A SAT like prover using word level information

Solvers for Boolean Satisfiabilily (SAT) are state-of-the-art to solve verification problems. But when arithmetic operations are considered, the verification performance degrades with increasing data-path width. Therefore, several approaches that handle a higher level of abstraction have been studied in the past. But the resulting solvers are still not robust enough to handle problems that mix word level structures with bit level descriptions. In this paper, we present the satisfiability solver SWORD — a SAT like solver that facilitates word level information. SWORD represents the problem in terms of modules that define operations over bit vectors. Thus, word level information and structural knowledge become available in the search process. The experimental results show that on our benchmarks SWORD is more robust than Boolean SAT, K⋆BMDs or SMT.

Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization

Advances in the chip manufacturing process impose new requirements for post-production test. Small Delay Defects (SDDs) have become a serious problem during chip testing. Timing-aware ATPG is typically used to generate tests for this kind of defects. Here, the faults are detected through the longest path. In this paper, a novel timing-aware ATPG approach is proposed which is based on Pseudo-Boolean Optimization (PBO) in order to leverage the recent advances in solving techniques in this field. Additionally, the PBO-based approach is able to cope with the generation of hazard-free robust tests by extending the problem formulation. As a result, the faults are detected through the longest robustly testable path, i.e. independently from other delay faults. Experimental results show that a hazard-free robust test can be efficiently found for most testable timing-critical faults without much reduction in path length.

Efficient Data Structures and Methodologies for SAT-Based ATPG Providing High Fault Coverage in Industrial Application

ATPG based on Boolean satisfiability (SAT) turned out to be a robust alternative to classical structural automatic test pattern generation (ATPG) algorithms performing very well especially for hard-to-detect faults but suffer from the overhead for easy-to-detect faults. In this letter, we propose new efficient data structures and methodologies for SAT-based ATPG. The novel incremental SAT solving technique dynamic clause activation which makes use of structural information using dedicated data structures forms the core of a new flexible SAT-based ATPG approach. Experimental results on large industrial circuits show a significant performance gain and a removal of the limitations. At the same time, the robustness of SAT-based ATPG can even be strengthened resulting in very high fault efficiency and increased fault coverage for transition faults.

As-Robust-As-Possible test generation in the presence of small delay defects using pseudo-Boolean optimization

Delay testing is performed to guarantee that a manufactured chip is free of delay defects and meets its performance specification. However, only few delay faults are robustly testable. For robustly untestable faults, non-robust tests which are of lesser quality are typically generated. Due to significantly relaxed conditions, there is a large quality gap between non-robust and robust tests. This paper presents a test generation procedure for As-Robust-As-Possible (ARAP) tests to increase the overall quality of the test set. Instead of generating a non-robust test for a robustly untestable fault, an ARAP test is generated which maximizes the number of satisfiable conditions required for robust test generation by pseudo-Boolean optimization. Additionally, the problem formulation is extended to incorporate the increased significance of small delay defects. By this, the likeliness that small delay defects invalidate the test is reduced. Experimental results on large industrial circuits confirm the quality gap and show that the generated ARAP tests satisfy a large percentage of all robustness conditions on average which signifies a very high quality.

Incremental Solving Techniques for SAT-based ATPG

Automatic test pattern generation (ATPG) based on the Boolean satisfiability (SAT) problem has recently been proven to be a beneficial complement to traditional methods. Efficient SAT techniques yield a robust fault classification. In this paper, we present methodologies to improve the efficiency of SAT-based ATPG. First, we give a detailed run time analysis of a state-of-the-art SAT-based ATPG tool. By only taking circuit partitions into account and applying incremental SAT solving, both SAT instance generation and SAT instance solving can be accelerated and the robustness of the ATPG process is increased. Besides the significant run time reduction of SAT-based ATPG, the methodology can additionally be used to improve the test set quality. The proposed techniques are applied for the stuck-at and for the transition fault model. A set of large industrial designs is used to show the efficiency of the approach.

A Highly Fault-Efficient SAT-Based ATPG Flow

ATPG based on Boolean Satisfiability (SAT) could be a promising alternative to structural test generation algorithms. This article proposes a SAT-based ATPG flow for generating high quality test patterns while applicable to large industry designs.

Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques

Due to the increased speed in modern designs, testing for delay faults has become an important issue in the post-production test of manufactured chips. A high fault coverage is needed to guarantee the correct temporal behavior. Todays ATPG algorithms have difficulties to reach the desired fault coverage due to the high complexity of modern designs. In this paper, we describe how to efficiently integrate the reuse of learned information into state-of-the-art SAT-based ATPG algorithms and, by this, reduce the number of unclassified faults significantly. For further reduction, a post-classification phase is presented. Experimental results for ATPG for delay faults on large industrial circuits show the robustness and feasibility of the approach.

Experimental Studies on SAT-Based ATPG for Gate Delay Faults

The clock rate of modern chips is still increasing and at the same time the gate size decreases. As a result, already slight variations during the production process may cause a functional failure. Therefore, dynamic fault models like the gate delay fault model are becoming more important. Meanwhile classical algorithms for test pattern generation reach their limits regarding run time and memory needs. In this work, a SAT-based approach to calculate test patterns for gate delay faults is presented. The basic transformation is explained in detail. The application to industrial circuits - where multi-valued logic has to be considered - is studied and experimental results are reported.