Stephen A. Szygenda

Use of Non-Linear Programming and Stochastic Modeling in the Medical Evaluation of Normal-Abnormal Liver Function

A model for Rose Bengal transport through the hepatobiliary system has been developed, and non-linear programming techniques have been used to derive the models parameters according to actual patient data. The model is then further analyzed as a Markov chain. A system of checks and balances, and measure of error, is discussed.

Timing analysis for digital fault simulation using assignable delays

The techniques to be described in this paper are generally applicable to any time domain, parallel fault, digital logic simulation system. The particular implementation was done on the CC-TEGAS3 system and quoted results are from this system. The first technique to be considered provides accuracy of fault simulation when using assignable nominal delays for different element types. The second technique provides for handling fault induced activity in a network, in such a way as to considerably reduce the amount of simulation time required.

Design validation: comparing theoretical and empirical results of design error modeling

To use simulation for design verification, designers need a confidence measure for a given set of simulation patterns, specifically for cases in which only a subset of the possible patterns is used. The authors derive a measure of design verification coverage based on the number of design errors detected in a theoretical analysis of a circuit. To verify the theoretical analysis, they simulate errors and compare the results.<<ETX>>

The simulation automation system (SAS); concepts, implementation, and results

The simulation automation system (SAS) was developed to provide an efficient simulation environment, by automating the entire simulation process. This system can be classified, by its salient unique features, into: automatic model generator (AMG), automatic simulator developer (ASD), and design error simulation and test system (DEST). The system can automatically generate multivalued simulation models and automatically develop various simulators, using domain specific automatic programming techniques. The automatic model generation feature can be used when a new model library is built or when an existing library is upgraded. The automatic simulator development feature allows a user who may not be knowledgeable about simulators, to easily develop unique simulators, which can be used for special purposes or special designs. SAS can also verify designs using the Design Error Simulation and Test System. It provides a confidence measure of the verification, as well as simulation results. When users are not satisfied with the confidence level achieved after simulation, they can automatically generate additional simulation patterns for design errors in order to achieve a higher confidence level. Using this approach, design verification time and cost can be considerably reduced, and an actual measure of verification is provided. Consequently, the design cycle can be considerably reduced. This is especially significant for large, complex systems. >

Exploiting component/event-level parallelism in concurrent fault and design error simulation

The paper describes the algorithm CON/sup 2/FERS, which exploits the event level and component level parallelisms in the concurrent technique for fault and design error simulation. This algorithm assumes asynchronous, message based operation with NORMA, and MIMD models of programming. A design verification tool based on this algorithm is developed with object oriented methodology using C++ and PVM. This implementation is executable on any Network of Workstations (NOW) and/or any general purpose parallel machine. The statistics on fault and error simulation performance and load balancing for some benchmark circuits are presented. Various experimental results of the effect of network and load on the performance of the CON/sup 2/FERS, and the applicability of the algorithm for the hardware acceleration of CFES are also presented.

Special purpose array processor for digital logic simulation

Digital logic and fault simulation of large VLSI circuits is one of the most compute-intensive tasks in digital analysis. This paper describes a special purpose time driven array processor for digital logic simulation. The new architecture uses a massively parallel processing element (PE) array in a SIMD architecture. Compiled event-driven technology and nominal transport delay timing analysis are used. A circuit to be simulated is levelized according to the delay time order at the preprocessing stage and the levelized circuit is mapped into a massively parallel PE array. Circuit comparisons show that the speedup of the new architecture is up to 8 times faster than the MARS accelerator and it can be higher for increased circuit size; while the hardware cost remains low.<<ETX>>

A mixed-level MOS logic simulator utilizing a new continuous strength algebra (CSAL)

A new evaluation method for logical MOS gates is presented. The approach is suitable for mixed-level simulation of gates and switches. A logical MOS gate models a driver-load transistor network, performing a Boolean logic function, in a static manner. The gate is normally represented by a Boolean expression, of which conventional evaluations at the gate level provide the signal level but not the signal strength of the gate output. In order to overcome this limitation, a new expression (compatible with the Boolean expression) is defined over a new continuous strength algebra (CSAL), and it is then evaluated to provide the signal level and strength for the gate output. This approach achieves gate-level computation speed by using the higher level of abstraction and switch-level accuracy by utilizing the new algebra.<<ETX>>

Deriving design guidelines for diagnosable computer systems

Diagnosable computer systems are designed to detect and isolate the faults that occur during system operation. A number of techniques are available to the system designer of diagnosable systems. This paper examines a number of these techniques and derives a set of design guidelines incorporating them.

MOVE: model verification system

The authors address the issue of model correctness in an automated model generating system for a CAD system. They have designed a verification system called the model verifier (MOVE) to solve this problem. This approach is based on observation that if there exists an error in the generated model, it is in the functional primitives or the signal interconnections. Therefore, to verify the model, functional correctness checking for primitives and connection correctness checking for interconnections between primitives are used. The reason for the use of two distinct approaches in functional checking is to verify the models efficiently by overcoming the limitations of two approaches and using some heuristics. The advantage of this method is that it can efficiently verify the models and can be used in a practical sense.<<ETX>>

Digital Systems Simulation

Early approaches to digital logic simulation were extremely expensive, difficult to use, and plagued with model inaccuracies. Todays simulators have overcome these problems to varying degrees. This situation, combined with the ever-increasing complexity of todays technology, has prompted the acceptance of digital logic simulation as a mandatory tool in most design automation systems.