Saghir A. Shaikh

Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring

This paper introduces a method that enables the diagnosis of embedded memories via test response compression and automatic bitmap recognition. The proposed method has been tested via simulation with various memory specifications, fail patterns and test algorithms; it has also been implemented in a 0.18 /spl mu/m CMOS test chip.

Test and debug of networking SoCs-a case study

This paper describes the test challenges faced and testability features implemented on Level Ones networking System on Chip (SoC), IXE2000. The IXE2000 SoC is a 20+ million transistor Layer 2/3/4 Switch with 24 10/100 Mbps and 2 1000 Mbps Ethernet ports, and a predominantly IP-based design. The chip had constraints in terms of both design time and total system costs, which added an extra burden on test. The paper discusses how these constraints led to the current testability solutions and debug features on the chip.

Practices in Mixed-Signal and RF IC Testing

Mixed-signal (analog and digital) testing and RF testing pose major cost and quality challenges to the development of high-speed wired and wireless network and communication ICs. This article presents a brief overview of common industry practices for testing mixed-signal and RF ICs. We also present examples of DFT and BIST techniques for wired and wireless transceivers. Finally, we discuss the testing challenges of system-in-package (SiP) products and selected DFT approaches in use today.

Maximizing wafer productivity through layout optimizations

Success of the fabless model has increased competition and has put pressure on design houses to reduce die costs. One method of cost reduction is the application of design for manufacturability (DFM) at the layout stage. Previously DFM has been applied to standard cell libraries and has been shown to lower die cost by 4.6%. This paper applies DFM to the routing. In particular this paper analyzes the effects of various routing options on wafer productivity and shows that if properly applied DFM can lead to a further die cost reduction of 9%.

Design of an experience-based assembly sequence planner for mechanical assemblies

This paper presents a design of an assembly sequence planner based on a “plan reuse” philosophy. Most of assembly planning research in the past has attempted to completely plan each problem from scratch. This research shows that stored cases of basic assembly configurations can be applied to a given assembly problem. It is observed that the number of such basic assembly configurations is quite small. The planner divides the assembly into a number of constituent configurations, which are called “loops”. These act as subgoals in its search for solutions. Plans retrieved for all subgoals are fused into a set of plans that are consistent with the constraints implied by each plan. Application specific constraints on the assembly are explicitly handled in the second phase of planning. Mechanisms for assembly representation and implementation details of the planner are also presented.

Manufacturability and testability oriented synthesis

This paper presents a case for new generation synthesis tools that incorporate manufacturability and testability as optimization factors in addition to traditional factors such as timing, die-area, and power. A suitable approach for manufacturability oriented synthesis is the interconnect field model, which estimates yield as a function of netlist attributes. Testability oriented synthesis encompasses various design-for-test (DFT), synthesis for testability, (SFT) and the high-level test synthesis (HLTS) techniques during the synthesis process.

IEEE standard 1149.6 implementation for a XAUI-to-serial 10-Gbps transceiver

The design, implementation and verification of IEEE standard1149.6 IP for a transceiver manufactured with 90 nm technology and using current mode logic (CML) are challenging because (i) CML has high operating frequency, (ii) CML has very low operating voltage range, and (iii) CML is inherently a differential type of circuitry. This work describes how major building blocks of IEEE standard1149.6 IP-such as input test receiver, boundary scan register containing new AC boundary scan cells, output test signal generation circuitry, and modified TAP controller-were implemented and verified. Third-party CAD tools typically used for IEEE standard 1149.1 IP generation were used for this implementation.

Exploiting component/event-level parallelism in concurrent fault and design error simulation

The paper describes the algorithm CON/sup 2/FERS, which exploits the event level and component level parallelisms in the concurrent technique for fault and design error simulation. This algorithm assumes asynchronous, message based operation with NORMA, and MIMD models of programming. A design verification tool based on this algorithm is developed with object oriented methodology using C++ and PVM. This implementation is executable on any Network of Workstations (NOW) and/or any general purpose parallel machine. The statistics on fault and error simulation performance and load balancing for some benchmark circuits are presented. Various experimental results of the effect of network and load on the performance of the CON/sup 2/FERS, and the applicability of the algorithm for the hardware acceleration of CFES are also presented.

Challenges in High Speed Interface Testing

There is a common trend towards the incorporation of Serial Interfaces into Systems-on-Chips (SoC), both for inter-chip and intra-chip high-bandwidth data transfers. Serial interfaces have the same channel medium drives as Parallel interfaces and provide increased data rates and fewer interconnects. High speed serial interfaces, such as SATA, Hyper- Transport, and PCI Express, are becoming pervasive in networking and in computer equipment. Some computer interfaces are converging to communications interfaces. Today, speeds for these serial interfaces range from 1.5 to 3.3 Gbps; in the near future, they will reach 6.4 Gbps and beyond (Figure 1).

Statistics on concurrent fault and design error simulation

Basic data of the nature presented here on fault and design error simulation processes have not been previously reported. Experiments are performed on c-sim, a gate level concurrent simulator developed at the University of Texas at Austin. Three types of statistics are considered: event based statistics, gate evaluation statistics and memory requirements. These statistics are important for design verification researchers and engineers for numerous reasons. For example, they help simulator developers tune up or optimize their concurrent simulators. They also fulfill the increasing need for experimental data concerning design error simulation. Most importantly, these statistics provide guidance to hardware accelerator designers in evaluating and comparing various design options.