Stephen Kilpatrick

Impact of electrode roughness on metal-insulator-metal tunnel diodes with atomic layer deposited Al2O3 tunnel barriers

Metal-insulator-metal (MIM) tunnel diodes on a variety of high and low work function metals with various levels of root-mean-square roughness are fabricated using high quality atomic layer deposited Al2O3 as the insulating tunnel barrier. It is found that electrode surface roughness can dominate the current versus voltage characteristics of MIM diodes, even overwhelming the impact of metal work function. Devices with smoother bottom electrodes are found to produce current versus voltage behavior with higher asymmetry and better agreement with Fowler-Nordheim tunneling theory, as well as a greater percentage of functioning devices.

Graphene Growth via Carburization of Stainless Steel and Application in Energy Storage

A modified version of the carburization process, a widely established technique used in the steel industry for case hardening of components, is used for the growth of graphene on stainless steel. Controlled growth of high-quality single- and few-layered graphene on stainless steel (SS) foils through a liquid-phase chemical vapor deposition (CVD) technique is reported. Reversible Li intercalation in these graphene-on-SS structures is demonstrated, where graphene and SS act as electrode and current collector, respectively, providing very good electrical contact. Direct growth of an active electrode material, such as graphene, on current-collector substrates makes this a feasible and efficient process for developing thin-film battery devices.

Stability and bias stressing of metal/insulator/metal diodes

The performance and stability of metal/insulator/metal tunnel diodes was investigated as a function of interfacial roughness using Al, Ir, Pt, and ultra-smooth amorphous multi-metal (ZrCuAlNi) bottom electrodes with uniform Al2O3 tunnel dielectrics deposited via atomic layer deposition. Current density versus field behavior and device yield were found to be a function of interfacial roughness with smoother electrodes exhibiting more ideal behavior and higher percentages of working devices. A preliminary investigation of DC bias stressed devices suggests that interfacial roughness plays a large role in stability and reliability as well.

Majority and minority carrier mobility behavior and device modeling of doped CVD monolayer graphene transistors

Wafer-scale graphene synthesized by Chemical Vapor Deposition (CVD) has the potential to enable numerous advanced device and system capabilities [1–3]. The typical reported carrier mobility of CVD graphene is significantly lower than exfoliated or on-SiC material due potentially to different impurity/doping levels and material quality. Elucidating the potential carrier scattering sources in metal catalyzed CVD graphene is essential for realizing high mobility material for both holes and electrons. We constructed field effect transistors using Cu catalyzed LPCVD synthesized p-type doped monolayer graphene and used direct electrical measurements under ambient and vacuum conditions to analyze some important physical aspects of the majority and minority carrier mobility behavior. We measured a dependency between shifting of the Dirac Point directed towards neutral levels under soft vacuum/annealing conditions and an increase in the extracted low-field carrier mobility. Reduction in the effective p-type “doping” of the graphene results in an increase of the carrier mobility of both the minority electrons and majority holes, with a stronger majority carrier dependency. The measured I–V characteristics of the devices are modeled (in the scattering limited regime) using a simple drift/diffusion model implemented in a continuum simulator. Using this model, the effective doping density, carrier concentration, and mobility are extracted for electrons and holes. Analysis of the energy dependency of the carrier mean-free-path for back-scattering, suggests that the hole mobility in this CVD material is limited by large levels of Coulomb scattering, whereas the electron mobility is limited by a combination of both Coulomb and other shorter-range scattering.

Carbon Nanotube - Substrate Interface Characteristics Studied via TEM

The unique properties of carbon nanotubes (CNTs), including their high current density, ballistic conductance, and high thermal conductivity, make them extremely attractive materials for electronic applications such as field emitters, sensors and nanoelectronic devices, and for thermal management structures [1]. Knowledge of the CNT/substrate interfacial characteristics is important in order to achieve controllable growth and the desired application-specific properties.

Densified Vertically-Aligned Carbon Nanotube Arrays by Chemical Vapor Infiltration

The densification of vertically-aligned carbon nanotube arrays into solid-like coatings is highly desirable for certain applications, including those requiring increased robustness or hardness, protection from oxygen at high temperatures and other damaging ambients, or increased effective thermal conductance. Chemical vapor infiltration (CVI) is a technique that essentially extends the commonly-used chemical vapor deposition process to the filling of networks of pores within a fibrous preform by altering the deposition kinetics toward a mass-transfer limited process. In this study, the CVI technique was utilized for filling the space around carbon nanotubes in vertically-aligned arrays on SiO2 substrates with a novel but simple approach. Nanotube growth was conducted using a vapor phase catalyst delivery method in a chemical vapor deposition chamber at 770 degC with a mixture of xylene and ferrocene vapors. Once the nanotube growth had ended, the conditions were altered to initiate the infiltration of carbon-containing species into the nanotube array, resulting in carbon deposition on the nanotubes. The extent of infiltration and location of the remaining porosity was determined using SEM analysis and microbalance measurements, for infiltration times up to 10 hours. The type of C-C bonding within the densified films was elucidated using Raman scattering. Vickers microhardness measurements were made to determine the hardness of carbon-densified nanotube arrays. These studies were largely motivated by the anticipated use of carbon nanotubes for on-chip thermal management on wide bandgap high-power semiconductor devices, optical devices, MEMS structures, and nanoscaled electronics