Stephen Strazdus

An embedded 32-b microprocessor core for low-power and high-performance applications

An embedded RISC microprocessor core fabricated in a six-layer metal 0.18-/spl mu/m CMOS process implementing the ARM/sup TM/ V.5TE instruction set is described. The core described is the first implementation of the Intel XScale Microarchitecture/sup TM/. The microprocessor core, which includes caches, memory management units, and a bus controller, comprises a hard-embedded block 16.77 mm/sup 2/ in size. The implementation is primarily custom logic in a variety of circuit styles. The processor dissipates 450 mW at 1.3 V, 600 MHz, and scales between 55 mW at 0.7 V, 200 MHz, and 900 mW at 1.65 V 800 MHz. Architectural performance is 1000 MIPS at 800 MHz with efficiency ranging from over 850 MIPS/W at 1.65 V to over 4500 MIPS/W at 0.75 V. Architectural and circuit design approaches for low power and high performance are described and measured results from the initial implementation are shown. The first implementation VLSI chip has a 3.3-V pin interface and supports a 0.75-1.65-V core voltage range.

A low-power 2.5-GHz 90-nm level 1 cache and memory management unit

The design of a 90-nm virtually addressed cache subsystem with separate 32-kB instruction and data caches is described. The circuits and microarchitecture are illustrated, including architecture level trace data validating low-power features and provisions to support snooping while maintaining the latency and power of virtual addressing. Low-power memory management unit design including a translation lookaside buffer with process identifier mapping is also described. Level 1 caches with support for high bandwidth, single cycle 256 bit fill and evict, as well as features for low power are also described. The design approaches are validated through both simulation and experimental results.

Optimization of High Tc Superconducting Microwave Planar Structures

This paper compares the characteristics of superconducting microstrip lines to those of inverted microstrip line with the aim of obtaining the optimal structure that suits certain applications. Characteristics of two high Tc superconducting planar structures on LaA103 are evaluated using a two-dimensional numerical code based on the two fluid model and the TMz mode solution. The losses in the superconducting strip as well as the dielectric losses are taken into consideration. Three structures of the same characteristic impedance are considered. It is shown that the inverted microstrip line has a more uniform current and magnetic flux-density distributions, and lower dielectric and conductor losses, which makes it well suited for high current transmission. Although the microstrip line has more dielectric and conductor losses, it has a higher Q factor due to the large energy stored in the dielectric substrate.