Stephen T. Flannagan

Two-13 ns-64K CMOS SRAM's with very low active power and improved asynchronous circuit techniques

64K/spl times/1 and 16K/spl times/4 CMOS SRAMs which achieve an access time of 13 ns and less than 12-mA active current at 10 MHz are described. A double-metal 1.5-/spl mu/m p-well process is used. A chip architecture with local amplification improves signal speed and data integrity. Address stability detection techniques are introduced as a method of assuring full asynchronicity over a wide range of conditions. A chip-select speed-up circuit allows high-speed access from a power-down mode. A memory cell design is presented which has improved layout efficiency (area of 189 /spl mu/m/SUP 2/), yet provides a very high cell ratio of 3:1 for signal stability and margin. Experimental results are presented which demonstrate full performance under address skews and other asynchronous input conditions. High-speed enable access and address access are observed over a wide range of operating conditions.

Two 64K CMOS SRAMs with 13ns access time

This report will cover the development of 64K×1 and 16K×4 CMOS SRAMS with access times of 13ns and power dissipation of 60mW at 10MHz. A 1.5μm double-metal, double-poly process was used. Array archtiecture allowing short lines, high-gain data path and asynchronous circuit techniques will be described.

8 ns CMOS 64 K*4 and 256 K*1 SRAMs

64 K*4 and 256 K*1 SRAMs with 8-ns access time and using a 1.0- mu m CMOS process are described. The circuits are designed with source-coupling techniques to achieve high-speed with small-signal swings, using only CMOS devices. A metal option permits selection of the 64 K*4 or 256 K*1 configuration. The same core architecture has also been used to generate *8 and *9 designs. One version achieves 3-ns output enable access time. SRAM speed-power ratio has traditionally been improved by array subdivision and address transition detection (ATD) to decrease current. However, for operation near 100 MHz, the advantage of ATD is diminished. The design described here removes ATD, allowing the row address to propagate statically. The resulting DC current is, countered with a strategy of (1) radically increasing array subdivisions and (2) exploiting small-signal techniques, preamplifiers, and current regulation. The core consists of 32 blocks with 128 rows and 64 columns per block.<<ETX>>