Stephen W. MacQuarrie

Development of an 18 × 18 mm package-on-package using C4NP flip chip attach and back side grind

While the use and benefits of package-on-package (PoP) assembly in industry have been well documented [1, 2, 3] innovative uses of this package technology are continually introduced. An 18 × 18 mm package-on-package has been developed for a flip chip die with Pb-free C4NP solder bumps [4,5] at 150 µm pitch using back side grind (BSG) processing of 300 mm diameter wafers. This lower package size was required by the large, 9.8 × 9.8 mm die, and the matching 16 × 16 mm memory device. Grinding the die thickness supports the low package height requisite in our customers assembly. This space saving package also provided fast access for the memory by mounting the memorys I/O in close proximity to the processors I/O. The overall height, from the bottom package landing pad to the top surface of the die, was established by the mating upper package memory module. Grinding the flip chip die very thin and limiting the underfill thickness on the chip backside presented challenges that were overcome through process development. Further process development was required for the dispense and cure of the underfill within the limited area available between the die edges and the first row of landing pads. The underfill dispense parameters used in production for other flip chip products are not suitable for this specific application. Multiple tests determined that something was needed to physically maintain the underfill in a specific area and to prevent any contaminations on the landing pads surface. The best option we found was to add an ink dam, very close to the first row of PoP pads, all around the chip. It was demonstrated that only a thin ink line was enough to stop the underfill flow. In addition to the underfill work, this package development effort successfully overcame package warpage challenges, while maintaining cost and reliability targets. The package warpage was measured and these reliability characteristics were demonstrated in typical stress testing.