Steven C. Bass

Expanding the range of convergence of the CORDIC algorithm

The limitations on the numerical values of the functional arguments that are passed to the CORDIC computational units are discussed, with a special emphasis on the binary, fixed-point hardware implementation. Research in the area of expanding the allowed ranges of the input variables for which accurate output values can be obtained is presented. The methods proposed to expand the range of convergence for the CORDIC algorithm do not necessitate any unwidely overhead calculation, thus making this work amenable to a hardware implementation. The number of extra iterations introduced in the modified CORDIC algorithms is significantly less than the number of extra iterations discussed elsewhere. This reduction in the number of extra iterations will lead to a faster hardware implementation. Examples demonstrate the usefulness of the methods in realistic situations. >

The application of bit-serial CORDIC computational units to the design of inverse kinematics processors

C.S.G. Lee and P.R. Chang (1986) have shown how the mathematical and nonlinear function evaluation operations involved in the inverse kinematic solution for a six-joint manipulator could be re-expressed and reordered so as to allow their evaluation by an interconnection of CORDIC processors. The present authors describe the use of specialized, dedicated CORDIC processors, implemented in bit-serial form, to construct an inverse kinematics computational unit on a single VLSI chip.<<ETX>>

Minimizing the number of delay buffers in the synchronization of pipelined systems

When designing a pipelined digital system, delay buffers (often implemented as shift registers) are usually introduced into the system in order to synchronize the various signals impinging on each and every processing element. By thus insuring that all related inputs to each processing element arrive at precisely the same time, additional memory for this purpose need not be included within the processing elements themselves. The design of these elements may therefore be carried out independently of the topologies of the systems within which they will ultimately appear. Clearly, any solution to this synchronization problem is not likely to be unique; that is, there will usually exist many combinations of buffer locations and lengths that can produce overall input data synchronization in a typical pipelined network. When selecting one solution from many available solutions, it is natural to observe that it would be beneficial to implement a solution that makes use of the minimum number of total delay buffer stages necessary to produce synchronization in order that the system hardware cost and complexity may be reduced. In this paper, we present a technique to solve this delay buffer problem in polynomial time. Unlike other polynomial-time methods, this approach solves both the pipeline synchronization and buffer minimization problems within a single formulation. Furthermore, this technique is readily extended to handle pipelined systems containing feedback loops as well as processing elements whose fanout loads are greater than one. It has been used in a synthesis design environment. >

Synthesis of musical tones based on the Karhunen-Loeve transform

A musical tone synthesis technique based on the Karhunen-Loeve (KL) transform is introduced. Currently, most additive synthesis methods are based on a truncated Fourier series representation. The computational load has been reduced considerably, compared to that of Fourier-based additive synthesis, by replacing the sinusoids with a smaller set of basis functions derived from KL statistical techniques. Algorithms are developed for the analysis of tones, yielding the basis functions and synthesis parameters. Energy compression in the KL basis functions is enhanced by a classification procedure applied to the tones to be synthesized. A high level of natural quality is achieved in tones synthesized with this method. >

An efficient implementation of singular value decomposition rotation transforms with CORDIC processors

Abstract One of the most frequently used operations in singular value decomposition (SVD) is the two-sided rotation transformation on 2 × 2 matrices. In order to achieve high performances for CORDIC SVD processors, a new method of carrying out the two-sided rotation transformation on 2 × 2 matrices is discussed here. With this new implementation, either the processing time or the hardware cost of SVD processors may be reduced by almost 50% when compared to those given by Cavallaro and Luk [Proc. SPIE, Real-Time Signal Processing IX, San Diego, CA, Aug. 1986, Vol. 698, pp. 45-53]

Digital tone generation system with slot weighting of fixed width window functions

An electronic musical instrument wherein purely digital techniques are utilized for generating the basic waveform train and also keying the waveform train so as to have the customary keying envelope with attack, sustain and decay portions. The wavetrain is a cyclically repeated series of four-term Blackman-Harris window functions, wherein there are preferably eight such functions in each series. A plurality of individual keying envelopes are generated by a piecewise linear technique, and these envelopes are assigned respectively to the waveforms in the series so that the relative amplitudes of the waveforms can change with time over the life of the tone. This results in modulating with time the harmonic content of the tone.

Bit-serial CORDIC circuits for use in a VLSI silicon compiler

The CORDIC algorithm is discussed, and modifications which have been found to make the basic algorithms more flexible are presented. Logic diagrams of circuits which implement the fixed-point computations of these modified CORDIC algorithms in a bit-serial fashion are introduced. This choice allows the hardware to be compact and regular, thus permitting the placement of many CORDIC processing elements on a single die.<<ETX>>

The Efficient Digital Implementation of Subtractive Music Synthesis

The coming generation of discrete-time organs can use subtractive synthesis to achieve considerable advantages over their present-day continuous-time counterparts.

Maximal solution of linear systems of equations and an application in VLSI

The system of linear equations Ax=b is considered in the case when the system contains dependencies and inconsistencies. A simple heuristic technique that seeks an x satisfying the maximum number of equations in the set Ax=b is developed. This problem arises naturally when considering the VLSI implementation of large systems of CORDIC (coordinate rotation digital computer) computational processors. This VLSI application is described, and results of the algorithm when applied to several realistic CORDIC systems are given.<<ETX>>

Efficient computation of mixed higher partials of digital filter transfer functions

A concise formula is derived for the computation of mixed higher partial derivatives of digital filter transfer functions with respect to any combination of multiplier coefficients. If only one multiplier coefficient is involved in the differentiation, our formula specializes to a recent result of Crochiere [1].