Steven D. Millman

Special applications of the voting model for bridging faults

A transistor-level examination of bridging faults and the resulting logic-level bridging fault model is described. Experiments with simulations and silicon demonstrate its accuracy. Previous work has demonstrated the accuracy and efficiency of the voting model for bridging faults. This paper presents a complete formal description of the voting model. In addition, simple solutions to special applications of the voting model which generalize its applicability are presented. These applications include the Byzantine Generals Problem, complex gate designs, and nonuniform transistor sizes. How to use Binary Decision Diagrams to compare the voting model to other fault models is also presented. Finally, delay tests are shown to be a poor means for detecting bridging faults. This work was done to show that the voting model, a logic-level model for bridging faults, accurately describes the behavior of real faults in real circuits. >

Diagnosing CMOS bridging faults with stuck-at, IDDQ, and voting model fault dictionaries

Fault dictionaries for the stuck-at fault model are not appropriate for diagnosing CMOS bridging faults. This paper shows that for CMOS circuits containing bridging faults, either IDDQ or the voting model is needed for correct diagnosis. However, a technique based upon the voting model that uses stuck-at fault dictionaries to diagnose bridging faults is described. When the traditional stuck-at fault technique is used, between 30-50% of the bridging faults resulted in a misleading diagnosis which indicated the presence of the failure on a fault-free node. In addition, as the stuck-at fault diagnostic ability of a test increased, the bridging fault diagnostic ability decreased.<<ETX>>

Standard cell library characterization for setting current limits for I/sub DDQ/ testing

Industry needs to move from a separate step of design for test to solving test issues as an integral part of the design process. The linking of design and test is also needed for I/sub DDQ/ testing, which is required for high quality products. A key issue is how to set the I/sub DDQ/ current limit to detect defective parts without rejecting defect-free parts. Increasing design efforts for accurate standard cell library characterization, especially with respect to power provide the answer. This paper describes a method for setting the I/sub DDQ/ limit based upon cell library characterization. Additionally, the method for iterating in on the final values is reviewed and contrasted with the benefits of the new method.