John M. Acken

Diagnosing CMOS bridging faults with stuck-at fault dictionaries

It is shown that the traditional approach to diagnosing stuck-at faults with fault dictionaries generated for stuck-at faults is not appropriate for diagnosing CMOS bridging faults. A novel technique for using stuck-at-fault dictionaries to diagnose bridging faults is described. Teradynes LASAR was used to simulate bridging and stuck-at faults in a number of combinational circuits, including parity trees, multiplexers, and the 74ASCI181 4-b, 16-function ALU (arithmetic and logic unit). When the traditional technique was used, between 30%-50% of the bridging faults were mis-diagnosed, with the presence of a failure indicated on a fault-free node. In addition, as the stuck-at-fault diagnostic ability of a test increased, the bridging fault diagnostic ability decreased. By use of the new technique. over 92% of the bridging faults in the circuits used for this research were diagnosed correctly and less than 4% led to misleading diagnoses.<<ETX>>

Testing for Bridging Faults (Shorts) in CMOS Circuits

The stuck-at fault model, which is commonly used with fault simulation, does not adequately evaluate the effects of bridging faults (shorts between adjacent signal lines) in CMOS circuits. Tests for bridging faults can be performed on automatic test equipment, and the test vectors can be evaluated using logic simulation.

MIPS-X: a 20-MIPS peak, 32-bit microprocessor with on-chip cache

MIPS-X is a 32-b RISC microprocessor implemented in a conservative 2-/spl mu/m, two-level-metal, n-well CMOS technology. High performance is achieved by using a nonoverlapping two-phase 20-MHz clock and executing one instruction every cycle. To reduce its memory bandwidth requirements, MIPS-X includes a 2-kbyte on-chip instruction cache. The authors provide an overview of MIPS-X, focusing on the techniques used to reduce the complexity of the processor and implement the on-chip instruction cache.

Accurate modeling and simulation of bridging faults

A transistor-level examination of bridging faults and the resulting logic-level bridging fault model are described. Experiments with simulations and silicon demonstrate its accuracy. It is shown how to determine the logic value resulting from a bridging fault. This leads to a novel approach for test pattern generation and fault simulation. It is pointed out that the voting model accurately describes the behavior of shorted nodes in CMOS custom digital circuits. The logic value of shorted nodes is equal to the logic value output by the circuit with the most current drive. The threat of an intermediate voltage is very slight; therefore, bridging faults result in valid logic values on the shorted nodes.<<ETX>>

Fault Model Evolution For Diagnosis: Accuracy vs Precision

This paper describes the evolution of accurate fault models, especially with respect to integrated circuit diagnosis. The difference between accuracy and precision is described. The solution to the Byzantine Generals problem is described using the voting model for CMOS bridging faults.

A cross section of the issues and research activities related to both information security and cloud computing

Cloud computing amplifies computer security issues that have proliferated with the growth of the Internet. A broad range of security research is being applied to cloud computing. This paper gives a description of cloud computing followed by a general description of information security issues and solutions, and a brief description of issues linking cloud computing with information security. Security solutions must make a trade-off between the amount of security and its performance cost and impact on the end-user experiences. This is accentuated in a cloud computing environment where users desiring different levels of security share the same resources. An essential issue for cloud computing is the perception of security, which is beyond the simple technical details of security solutions. This paper includes a list of a few keyinformation security challenges that also present significant research opportunities. Solving these key problems will encourage the widespread adoption of cloud computing.

Special applications of the voting model for bridging faults

A transistor-level examination of bridging faults and the resulting logic-level bridging fault model is described. Experiments with simulations and silicon demonstrate its accuracy. Previous work has demonstrated the accuracy and efficiency of the voting model for bridging faults. This paper presents a complete formal description of the voting model. In addition, simple solutions to special applications of the voting model which generalize its applicability are presented. These applications include the Byzantine Generals Problem, complex gate designs, and nonuniform transistor sizes. How to use Binary Decision Diagrams to compare the voting model to other fault models is also presented. Finally, delay tests are shown to be a poor means for detecting bridging faults. This work was done to show that the voting model, a logic-level model for bridging faults, accurately describes the behavior of real faults in real circuits. >

Cloud Workload Characterization

Abstract This paper describes various computer system workloads and relates them to their underlying resource utilization. Specifically, the paper concentrates on Cloud workload characterization based upon issues, capabilities, and technologies surrounding the categories from the multiple points of view of the various players involved in Cloud Computing. The relationship is established between the categories and key limiting underlying technologies, and the dynamic and measurable low-level metrics and measurements that are used to detect and reduce resource contention, and identify category changes during run-time. Research questions are posed on dynamic low-level measurements and a usage case example with high performance computing (HPC) clusters. The Cloud workload categories can provide a basis for common communication for various viewpoints from players, including facility managers, Cloud IT or service providers, Cloud users, consumers, IT managers, and hardware vendors. This common communication tool will facilitate better service-level agreements (SLAs), capital purchase decisions, and future computer architecture design-decisions.

Standard cell library characterization for setting current limits for I/sub DDQ/ testing

Industry needs to move from a separate step of design for test to solving test issues as an integral part of the design process. The linking of design and test is also needed for I/sub DDQ/ testing, which is required for high quality products. A key issue is how to set the I/sub DDQ/ current limit to detect defective parts without rejecting defect-free parts. Increasing design efforts for accurate standard cell library characterization, especially with respect to power provide the answer. This paper describes a method for setting the I/sub DDQ/ limit based upon cell library characterization. Additionally, the method for iterating in on the final values is reviewed and contrasted with the benefits of the new method.

A 32b microprocessor with on-chip 2Kbyte instruction cache

A Reduced Instruction Set Computer with a 5-stage pipeline implemented with 150K transistors on an 8mm×8.5mm chip in a 2μm, 2 layer metal CMOS process, will be reported. At operational frequency of 20MHz, a 12MIPS performance has been achieved.