Steven E. Wells

A 90-ns one-million erase/program cycle 1-Mbit flash memory

Describes the design and performance of a 245-mil/sup 2/ 1-Mbit (128K*8) flash memory targeted for in-system reprogrammable applications. Developed from a 1.0- mu m EPROM-base technology, the 15.2- mu m/sup 2/ single-transistor EPROM tunnel oxide (ETOX) cell requires only 42 percent of the area required by the previous 1.5- mu m device. One of the most significant aspects of this 1-Mbit flash memory is the one-million erase/program cycle capability. The 1-Mbit memory exhibits 90-ns read access time while the reprogramming performance gives a 900-ms array erase time and a 10- mu s/byte programming rate. Ample erase and program margins through one-million erase/program cycles are guaranteed by the internal verify circuits. Column redundancy is implemented with the utilization of flash memory cells to store repaired addresses. >

An in-system reprogrammable 32 K*8 CMOS flash memory

The authors describe the design and performance of a 192-mil/sup 2/ 256 K (32 K*8) flash memory targeted for in-system reprogrammable applications. Developed from a 1.5 mu m EPROM base technology with a one-transistor 6*6- mu m/sup 2/ cell, the device electrically erases all cells in the array matrix in 200 ms and electrically programs at the rate of 100 mu s/byte typical. The read performance is equivalent to comparable-density CMOS EPROM devices with a chip-enable access time of 110 ns at 30-mA active current consumption. A command-port interface facilitates microprocessor-controlled reprogramming capability. Device reliability has been increased over byte-alterable EEPROMs by reducing the program power supply to 12 V. Cycling endurance experiments have demonstrated that the device is capable of more than 10000 erase/program cycles. >

Flash solid-state drive with 6 MB/s read/write channel and data compression

A 42-MB 2.5-in drive that includes a thirty-Mb device flash array, an embedded processor, and an interface ASIC (application-specific integrated circuit) is described. The 0.7- mu m standard-cell ASIC contains drive interface circuitry, a 4-port buffer manager, a flash interface, and a Lempel-Ziv-type hardware compressor. The flash device architecture is optimized for cost-effective high-density systems. Overall system performance is compared to that of a typical 2.5-in drive. Drive read timing with parallel host, sector buffer, and flash transfer is shown.<<ETX>>

A 90 ns 100 K erase/program cycle megabit flash memory

An electrically erasable, reprogrammable, 90-ns 1-Mb flash memory capable of greater than 100000 erase/program cycles is described. The memory implements a command port and an internal reference voltage generator, allowing microprocessor-controlled reprogramming. The 90-ns access time results from the 95- mu A memory cell current, low resistance polysilicide word lines, advanced scaled periphery transistors, and a di/dt optimized data-out buffer. Using CMOS inputs, power dissipation is 40 mW in the active state and 20 mu W in standby. The memory electrically erases in 900 ms and programs at the rate of 10 mu s/byte. The device contains thirty-two columns of redundant elements and utilizes flash memory cells to store the address of repaired columns. The memory was fabricated on a 1- mu m double-poly n-well CMOS process. A typical cell erase/program V/sub t/ margin is shown as a function of the number of reprogramming cycles. After 100000 cycles there is still a 2.5-V program-read margin to ensure data retention. Device parameters are listed.<<ETX>>