Steven M. Burns

Placement and routing tools for the Triptych FPGA

Field-programmable gate arrays (FPGAs) are becoming an increasingly important implementation medium for digital logic. One of the most important keys to using FPGAs effectively is a complete, automated software system for mapping onto the FPGA architecture. Unfortunately, many of the tools necessary require different techniques than traditional circuit implementation options, and these techniques are often developed specifically for only a single FPGA architecture. In this paper we describe automatic mapping tools for Triptych, an FPGA architecture with improved logic density and performance over commercial FPGAs. These tools include a simulated-annealing placement algorithm that handles the routability issues of fine-grained FPGAs, and an architecture-adaptive routing algorithm that can easily be retargeted to other FPGAs. We also describe extensions to these algorithms for mapping asynchronous circuits to Montage, the first FPGA architecture to completely support asynchronous and synchronous interface applications.

An FPGA for implementing asynchronous circuits

Field-programmable gate arrays are a dominant implementation medium for digital circuits, especially for glue logic. Unfortunately, they do not support asynchronous circuits. This is a significant problem because many aspects of glue logic and communication interfaces involve asynchronous elements, or require the interconnection of synchronous components operating under independent clocks. We describe Montage, the first FPGA to explicitly support asynchronous circuit implementation, and its mapping software. Montage can be used to realize asynchronous interface circuits or to prototype complete asynchronous systems, thus bringing the benefits of rapid prototyping to asynchronous design. Unfortunately, implementation media for asynchronous circuits and systems have not kept up with those for the synchronous world. Programmable logic devices do not include the special non-digital circuits required by asynchronous design methodologies (e.g., arbiters and synchronizers) nor do they facilitate hazard-free logic implementations. This leads to huge inefficiencies in the implementation of asynchronous designs as circuits require a variety of seperate devices. This has caused most asynchronous designers to focus on custom or semi-custom integrated circuits, thus incurring greater expense in time and money. The net effect has been that optimized and robust asynchronous circuits have not become a part of typical system designs. The asynchronous circuits that must be included are usually designed in an ad-hoc manner with many underlying assumptions. This is a highly error- prone process, and causes implementations to be unnecessarily delicate to delay variations. Field-programmable gate arrays, one of todays dominant media for prototyping and implementing digital circuits, are also inappropriate for constructing more than the simplest asynchronous interfaces. They lack the critical elements at the heart of todays asynchronous designs. Unfortunately, resolving this problem is not just a simple matter of adding these elements to the programmable array. The FPGA must also have predictable routing delay and must not introduce hazards in either the logic or routing. Futhermore, the mapping tools must also be modified to handle asynchronous concerns, especially the proper decomposition of logic to fit into the programmable logic blocks and the proper routing of signals to ensure that required timing relationships are met. Ideally, we need an FPGA that can support both synchronous and asynchronous circuits with comparable efficiency. As a step in this direction we present Montage, an integrated system of FPGA architecture and mapping software designed to support both asynchronous circuits and synchronous interfaces. The architecture provides circuits with hazard-free logic and routing, mutual exclusion elements to handle metastability, and methods for initializing unclocked elements. The mapping software generates placement and signal routing sensitive to the timing demands of asynchronous methods. With these features, the Montage system forms a prototyping and implementation medium for asynchronous designs, providing asynchronous circuits with a powerful tool from the synchronous designers toolbox.

The Triptych FPGA architecture

Field-programmable gate arrays (FPGAs) are an important implementation medium for digital logic. Unfortunately, they currently suffer from poor silicon area utilization due to routing constraints. In this paper we present Triptych, an FPGA architecture designed to achieve improved logic density with competitive performance. This is done by allowing a per-mapping tradeoff between logic and routing resources, and with a routing scheme designed to match the structure of typical circuits. We show that, using manual placement, this architecture yields a logic density improvement of up to a factor of 3.5 over commercial FPGAs, with comparable performance. We also describe Montage, the first FPGA architecture to fully support asynchronous and synchronous interface circuits.

An algorithm for exact bounds on the time separation of events in concurrent systems

Determining the time separation of events is a fundamental problem in the analysis, synthesis, and optimization of concurrent systems. Applications range from logic optimization of asynchronous digital circuits to evaluation of execution times of programs for real-time systems. We present an efficient algorithm to find exact (tight) bounds on the separation time of events in an arbitrary process graph without conditional behavior. This result is more general than the methods presented in several previously published papers as it handles cyclic graphs and yields the tightest possible bounds on event separations. The algorithm is based on a functional decomposition technique that permits the implicit evaluation of an infinitely unfolded process graph. Examples are presented that demonstrate the utility and efficiency of the solution. The algorithm will form a basis for exploration of timing-constrained synthesis techniques. >

Testing asynchronous circuits: a survey

Asynchronous circuit design has been studied for decades, but it has only recently been feasible to construct large and efficient asynchronous systems. The inherent differences between asynchronous and synchronous circuits, primarily that asynchronous circuits do not have a global clock, necessitate a review of the testing techniques used for synchronous circuits and a re-evaluation of the trade-offs involved. This paper surveys different techniques for checking whether an asynchronous circuit has fabrication defects. These techniques include approaches to self-checking design, methods for test generation, design for testability, and delay test of asynchronous circuits.

Bounded delay timing analysis of a class of CSP programs with choice

We extend our technique for determining exact time separation of events in systems with just concurrency to a restricted but still useful class of systems with both choice and concurrency. Such a system is described using a CSP program (including Martins probe operator) with the restrictions that the communication behavior is data-independent, that there is no OR-causality, and that guard selection is either completely free or mutually exclusive. Such a CSP program is transformed into a safe Petri net. Interval time delays are specified on the places of the net. The timing analysis we perform is, for all possible timed executions of the system, determine the extreme separations in time for all occurrences of specified events. We formally define this problem, propose an algorithm for its solution, and apply the algorithm to an example program.

MONTAGNE: An FPL for Synchronous and Asynchronous Circuits

Field-programmable gate arrays are frequently used to implement system interfaces and glue logic. However, there has been little attention given to the special problems of these types of circuits in FPGA architectures. In this paper we describe Montage, a Triptych-based FPGA designed for implementing asynchronous logic and interfacing separately-clocked synchronous circuits. Asynchronous circuits have different requirements than synchronous circuits, which make standard FPGAs unusable for asynchronous applications. At the same time, many asynchronous design methodologies allow components with greatly different performance to be substituted for one another, making a design environment which migrates between FPGA, MPGA, and semi-custom implementations very attractive. Similar problems also exist for interfacing separately-clocked synchronous circuits. We discuss these problems, and demonstrate how the Montage FPGA satisfies the demands of these classes of circuits.

General conditions for the decomposition of state holding elements

A fundamental problem in the design of speed-independent asynchronous circuits is the decomposition or splitting up of high-fanin operators into two or more lower-fanin operators. In this paper, we develop general techniques to decided whether a particular decomposition of an arbitrary state-holding or combinational element into two elements with an belated internal signal is correct. These techniques are extended to determine efficiently all legal decompositions in a parameterized family.

Practical applications of an efficient time separation of events algorithm

Determining the time separation of events is a fundamental problem in the analysis, synthesis, and optimization of concurrent systems. We present results of applying an efficient algorithm to solve this problem of three different application domains. These are: analysis of instruction execution times of an asynchronous multiprocessor, analysis of a high-performance mixed asynchronous/synchronous communication interface, and isochronic fork analysis in asynchronous circuit synthesis. The algorithm we use yields exact (tight) bounds on the separation time of events in an arbitrary process graph without conditional behavior. This class of graphs is quite large and includes graphs that are not strongly connected. The algorithm is based on a functional decomposition technique that permits the implicit evaluation of an infinitely unfolded process graph.

Efficient Timing Analysis of a Class of Petri Nets

We describe an algebraic technique for performing timing analysis on a restricted class of Petri nets with interval time delays specified on the places of the net. The timing analysis we perform determines the extreme separation in time between specified occurrences of pairs of transitions for all possible timed executions of the system. We present the details of the timing analysis algorithm and demonstrate polynomial running time on a non-trivial parameterized example. Petri nets with 3000 nodes and 1016 reachable states have been analyzed using these techniques.