Steven S. Poon

New considerations for MOSFET power clamps

Two ESD clamp circuit design techniques have been developed to reduce cell size and to combat the effects of gate leakage that have become significant in recent generations of digital CMOS process technology. Such clamps have proven to be able to withstand HBM stresses of 6kV and CDM pulses of 1.2kV.

Shielded cable discharge induces current on interior signal lines

Cable discharge event (CDE) stress to interior lines for shielded cables is measured and simulated. A W-shaped induced current pulse can appear on the interior lines due to discharge of the shield. Time domain analysis of the W-pulse and related conditions are discussed.

Using coupled transmission lines to generate impedance-matched pulses resembling charged device model ESD

A quarter-wave directional coupler plus ordinary transmission line pulsing (TLP) can create short pulses resembling charged device model (CDM) ESD. Pulse rise time often relates to the couplers center frequency and can thereby be stabilized. It is shown that for a voltage step of a given size, yet with arbitrary waveform, the net amount of coupled charge (the charge packet) is constant and depends only on fixed coupler parameters. This property of Z-matched coupled lines has wider implications. High voltage couplers can be made from coaxial cable or from stripline. Some of these designs are described, tested, and compared to computer simulations of coupled lines.

Total charge theorem for directional couplers and Z-matched coupled lines

It is proven that, in a two-line directional coupler of conventional design, the response to a voltage step on the input is a net amount of coupled charge on the output that is constant, and depends only on fixed properties of the coupler and the size of the voltage step, not on the waveform. This general property of Z-matched coupled lines is useful for pulse creation, and provides insight into certain memory bus techniques that use directional couplers for impedance-matched data transmission.

Methods for designing low-leakage ESD power supply clamps

Abstract Low-power semiconductor components require minimizing leakage currents including those from ESD protection circuits. Here, MOSFET ESD power clamps with substantial leakage reduction over previous approaches are presented. Designs are described for core logic circuits and for I/O applications where supply voltages exceed what single gate oxides can reliably sustain.

Using Coupled Transmission Lines to Generate Impedance-Matched Pulses Resembling Charged Device Model ESD

A quarter-wave directional coupler plus ordinary transmission line pulsing (TLP) can create short pulses resembling charged device model (CDM) electrostatic discharge (ESD). Pulse rise time often relates to the couplers center frequency and can thereby be stabilized. It is shown that for a voltage step of a given size, yet with arbitrary waveform, the net amount of coupled charge (the charge packet) is constant and depends only on fixed coupler parameters. This property of Z-matched coupled lines has wider implications. High-voltage couplers can be made from coaxial cable or from stripline. Some of these designs are described, tested, and compared to computer simulations of coupled lines

A full-chip ESD simulation flow

An ESD simulation flow that has been demonstrated on 14 nm products is described. Due to Moores Law, ESD protection devices are having an increasingly large impact on silicon area, power, and capacitance. A number of real-world examples demonstrating how the simulation flow improved these areas are provided.