Timothy J. Maloney

Novel clamp circuits for IC power supply protection

Biased and terminated p-n-p transistor chains are made from floating n-wells in p-substrate CMOS and used for power supply ESD clamps. The p-n-p gain may allow a compact termination circuit to be used, resulting in a stand-alone clamp. Bipolar p-n-p action accounts for unwanted low-voltage conduction as well as for very desirable clamping of power supply overvoltages. Bias networks are used to prevent excessive leakage at high temperature. These devices are becoming crucial to success in ESD product testing of CMOS integrated circuits.

Stacked PMOS clamps for high voltage power supply protection

Large PMOS FETs with multiple gates can be arranged to provide ESD protection to high voltage on-chip power supplies in submicron CMOS integrated circuits. These clamps divide the supply voltage among several gate oxides; the circuitry accompanying the large series FETs provides near-maximum gate drive during ESD for high pulsed current. Layouts are densely packed because minimum dimensions can be used and because no contact is needed between the stacked gates. The high voltage designs are extensions of the large PMOS FET ESD clamps and timed drive circuitry that are used to clamp ordinary on-chip power supply lines.

ESD on CHMOS Devices - Equivalent Circuits, Physical Models and Failure Mechanisms

Using new techniques it is possible to construct an EOS/ESD equivalent circuit of a product. Location of energy dissipation during an EOS/ESD event is determined by a pulsed near infrared technique. Rules for predicting location of ESD dissipation are defined. N+-P-N+ structures and n-channel transistors suffer from a current lock-on effect, which is apparently caused by a runaway oxide trapping mechanism. Different failure mechanisms are observed at narrow and wide pulse widths. Hot electron induced damage occurs under mechanical handling conditions. On CMOS outputs the n-channel device absorbs most of the ESD, and is very fragile.

Designing on-chip power supply coupling diodes for ESD protection and noise immunity☆

Abstract Noise is a major concern in VLSI systems as it compromises system performance and reliability. It has often become essential to decouple the noisy periphery from the core supplies. However, due to parasitic diodes some coupling is maintained. The ESD diodes required to provide robust current paths for ESD zaps may exacerbate this coupling. This paper examines how these diodes couple transient noise from the peripheral power supplies to the core power supplies during circuit operation, and how such considerations influence diode clamp design. This paper reports on noise coupling simulations and sets upper and lower limits on the number of diodes that may be used. These are based on operating and burn-in conditions and on fundamental diode properties, including temperature effects. In another context, N + to substrate diode clamping can have benefits. Most pad protection devices have a single parasitic diode to the substrate, meaning that when a signal comes to it from a low impedance driver and there is driver-line impedance mismatch, the ringing is forced negative and is suppressed by turn-on of the diode. But the decay of that signal can result in some curious effects, for which simulations and experimental measurements will be discussed.

New considerations for MOSFET power clamps

Two ESD clamp circuit design techniques have been developed to reduce cell size and to combat the effects of gate leakage that have become significant in recent generations of digital CMOS process technology. Such clamps have proven to be able to withstand HBM stresses of 6kV and CDM pulses of 1.2kV.

Integrated circuit metal in the charged device model: bootstrap heating, melt damage, and scaling laws

Abstract Charged-device model electrostatic discharge (CDM ESD) stresses thin metal lines heavily because of strong I 2 R heating, resulting in a wider linewidth requirement as thin AlCu is integrated into multilayer metal systems. Metal heating during a CDM event is shown to strongly depend on device capacitance and on temperature coefficient of resistance.

Designing power supply clamps for electrostatic discharge protection of integrated circuits

Power supply electrostatic discharge (ESD) clamping is needed to protect the IC power supply as well as to provide convenient discharge paths for ESD currents, and thereby simplify the total design problem. A variety of methods are reviewed and explored, notably those employing diodes or field effect transistor (FETs) built in bulk complementary metal-oxide semiconductor (CMOS) technology and avoiding avalanche behavior. Power clamping can occur across comparable power supplies or between a power supply and ground; there are diode and FET methods for each. Designs extend to clamping for mixed voltage supplies on a single chip, including power supplies above the gate oxide tolerance. New designs and results for power clamps based on PMOS FETs are presented for the first time.

Protection of high voltage power and programming pins

Electrostatic discharge (ESD) protection of an inte- grated circuits (ICs) high voltage power pins is achieved without damage to thin oxides by dividing the steady-state voltage and arranging weak forward bias of the diodes of a cantilever clamp. Also, programming pins are protected by cantilever clamps of various kinds, including some which turn on when breakdown is detected and turn off after is powered up.

Shielded cable discharge induces current on interior signal lines

Cable discharge event (CDE) stress to interior lines for shielded cables is measured and simulated. A W-shaped induced current pulse can appear on the interior lines due to discharge of the shield. Time domain analysis of the W-pulse and related conditions are discussed.

Gate oxide reliability characterization in the 100ps regime with ultra-fast transmission line pulsing system

An Ultra-fast Transmission Line Pulsing (UFTLP) system is demonstrated. Very short pulses down to 40 ps with a large voltage range (up to 100 V in this work) can be generated. Gate oxide reliability is quantified in the 100 ps regime for the first time. Hard and soft breakdown transitions are clearly captured, and the results explain why some logic cells still function after breakdown events.