Su-Kyung Yoon

Data Classification Management with its Interfacing Structure for Hybrid SLC/MLC PRAM Main Memory

This research aims to design a new phase-change RAM (PRAM)-based main memory structure, supporting the advantages of PRAM while providing performance similar to that of conventional DRAM main memory. To replace conventional DRAMs with non-volatile PRAMs as the main memory components, comparable memory access latency, overall cost, power dissipation, and memory cell endurance should be supported. For these goals, we propose a new main memory system consisting of a DRAM converter and an array of single-level cell (SLC)/multi-level cell (MLC) PRAMs. The DRAM converter consists of an aggressive fetching superblock buffer to assure better use of spatial locality and a selective filtering buffer for better use of temporal locality. The array of the SLC/MLC hybrid PRAM structure includes a combination of SLC and MLC PRAMs to enhance the lifetime of the MLC PRAM main memory and hide asymmetric read/write access latency. The proposed structure is evaluated by a trace-driven simulator using SPEC CPU 2006 and SPLASH-2 traces. Experimental results show that the proposed DRAM converter can reduce the miss rate by ∼37% and write count by ∼55% in comparison with the uniform buffer case. Also, the SLC/MLC PRAM with DRAM converter shows performance in terms of access latency and power consumption close to that of the conventional memory architecture. Thus, our proposed memory architecture can be used to replace the current DRAM-based main memory system.

A New Memory-Disk Integrated System with HW Optimizer

Current high-performance computer systems utilize a memory hierarchy of on-chip cache, main memory, and secondary storage due to differences in device characteristics. Limiting the amount of main memory causes page swap operations and duplicates data between the main memory and the storage device. The characteristics of next-generation memory, such as nonvolatility, byte addressability, and scaling to greater capacity, can be used to solve these problems. Simple replacement of secondary storage with new forms of nonvolatile memory in a traditional memory hierarchy still causes typical problems, such as memory bottleneck, page swaps, and write overhead. Thus, we suggest a single architecture that merges the main memory and secondary storage into a system called a Memory-Disk Integrated System (MDIS). The MDIS architecture is composed of a virtually decoupled NVRAM and a nonvolatile memory performance optimizer combining hardware and software to support this system. The virtually decoupled NVRAM module can support conventional main memory and disk storage operations logically without data duplication and can reduce write operations to the NVRAM. To increase the lifetime and optimize the performance of this NVRAM, another hardware module called a Nonvolatile Performance Optimizer (NVPO) is used that is composed of four small buffers. The NVPO exploits spatial and temporal characteristics of static/dynamic data based on program execution characteristics. Enhanced virtual memory management and address translation modules in the operating system can support these hardware components to achieve a seamless memory-storage environment. Our experimental results show that the proposed architecture can improve execution time by about 89% over a conventional DRAM main memory/HDD storage system, and 77% over a state-of-the-art PRAM main memory/HDD disk system with DRAM buffer. Also, the lifetime of the virtually decoupled NVRAM is estimated to be 40% longer than that of a traditional hierarchy based on the same device technology.

Optimized Memory-Disk Integrated System with DRAM and Nonvolatile Memory

New nonvolatile memory devices can overcome the high-energy consumption, volatility, and density scaling limit of dynamic RAM (DRAM). With these advantages, next-generation nonvolatile memory devices can use both working memory and persistent storage simultaneously. In this study, we horizontally arrange DRAM, phase change memory (PCM), and flash memories as a single compound layer of working and storage space for a memory-disk integrated system (MDIS). The MDIS architecture consists of a static data buffer, DRAM/PCM/Flash hybrid array, and its associated MDIS management module. The static data buffer is placed between the last-level cache and DRAM/PCM/Flash hybrid array to reduce the performance gap. In the DRAM/PCM/Flash hybrid array, DRAM space and a portion of PCM space are used for dynamic data, and the remaining portion of PCM space and flash memory are used for static data including program text and data segments. Based on our simulation results, dynamic access latency of a dynamic area with 128 MB DRAM of space is faster than the MDIS with a PCM-only array model by approximately 5.5 times. Furthermore, the results show that the total execution time of our proposed model with 128-MB DRAM space improves speed by 4.3 times compared to conventional memory-storage system, respectively.

A Unified Buffering Management with Set Divisible Cache for PCM Main Memory

This research proposes a phase-change memory (PCM) based main memory system with an effective combination of a superblock-based adaptive buffering structure and its associated set divisible last-level cache (LLC). To achieve high performance similar to that of dynamic random-access memory (DRAM) based main memory, the superblock-based adaptive buffer (SABU) is comprised of dual DRAM buffers, i.e., an aggressive superblock-based pre-fetching buffer (SBPB) and an adaptive sub-block reusing buffer (SBRB), and a set divisible LLC based on a cache space optimization scheme. According to our experiment, the longer PCM access latency can typically be hidden using our proposed SABU, which can significantly reduce the number of writes over the PCM main memory by 26.44%. The SABU approach can reduce PCM access latency up to 0.43 times, compared with conventional DRAM main memory. Meanwhile, the average memory energy consumption can be reduced by 19.7%.

Selective data buffering module for unified hybrid storage system

A new design methodology is aggressively considered on conventional memory hierarchy structure because of newly emerging non-volatile memory technologies. This paper presents a unified single memory structure that merges existing main memory layer and secondary storage layer together. This structure eliminates conventional page swap operations causing significant performance degradation and supports fast program execution time. The unified single memory structure consists of a selective data buffering module and a hybrid array of PCM (phase change memory) and NAND Flash storage. This hybrid array of non-volatile memories is formed as a single memory-disk integrated storage space which can be logically divided into static and dynamic spaces. This research is to design a selective data buffering structure to reduce asymmetric read/write latencies and increase the lifetime of hybrid storage based on PCM and NAND Flash. The proposed structure is compared with the interfacing adapter structure of the memory-disk integrated system. Experimental results show that the hit rate of the selective data buffering structure increases by 90.5%, compared with the NVPO under the memory-disk integrated system [10], which shows 76.9% hit rate. The access latency is also improved by around 20.6%.

Designing virtual accessing adapter and non-volatile memory management for memory-disk integrated system

This paper presents a new memory hierarchy system using next-generation non-volatile memory devices merging a conventional main memory layer and a disk storage layer into a single memory layer, called a memory-disk integrated system (MDIS). In the MDIS, files are stored in MDIS storage and accessed in place as if they are in conventional DRAM main memory without any duplication between the main memory and secondary storage. The MDIS comprises three components: a virtual accessing adapter (VAA), an array of non-volatile hybrid memory (NVHM), and its associated virtual memory management module. The NVHM can be divided into two spaces-specifically, static and dynamic spaces-to support conventional memory management. Further, the VAA comprises four small buffers that support static and dynamic virtualization according to program execution characteristics. Experimental results show that the read/write load traffics for the proposed MDIS can be reduced by about 73% as compared with the cases of conventional main memory system. In addition, access latency of non-volatile hybrid memory is reduced by 51%.

Fast bootstrapping method for the memory-disk integrated memory system

This research is to design system software modules for main memory-disk integrated system. To utilize many useful features of recent non-volatile memory, a horizontal memory hierarchy should be considered as a new approach. Main objective of this study is to design an optimized bootstrap method for the integrated memory-disk system, along with compatibility with conventional bootloader and operating system. In this memory-disk integrated system, stored files and data are accessed in place reducing duplication between the main memory and storage. Thus, previous booting sequence of loading bootstrap and operating system from secondary storage to main memory should be changed to reflect the architectural change. Our proposed technique provides compatibility with conventional system software and fast booting time by utilizing prominent advantages of the integrated memory-disk system and optimizing booting sequence for this system. To implement this method, we modified BIOS (basic input/output system) to change booting from integrated memory-disk system. We used QEMU machine emulator to simulate the proposed booting method. Our experimental results show that the proposed bootstrap method can reduce the number of instructions to execute by around ten millions, resulting in fast boot performance and keeping the core of the bootloader.

Harmonized memory system for object-based cloud storage

A new storage system that integrates non-volatile with conventional memory, a harmonized memory system (HMS) for object-based cloud storage, is proposed. The system overcomes IO bottlenecks when managing large amounts of metadata and transaction logs and is composed of five modules. The first, the harmonized memory supervisor, is a translation layer for accessing the harmonized array module. It manages address translation, address mapping by page linking, and wear leveling. The second, the harmonized array module, is divided into dynamic and static areas composed of DRAM, and PCM together with NAND flash memory, respectively. The harmonized memory migration engine and data pattern predictor, which anticipates future data flow, are designed to maximize the effectiveness of the PCM array area. The harmonized logging conductor processes the log between the PCM array and NAND flash areas. Experimental results show the total execution time and energy consumption of HMS is 5.77 faster and 4.27 times lower, respectively, than the conventional DRAM-HDD model for object-based storage workloads.

Self-Adaptive Filtering Algorithm with PCM-Based Memory Storage System

This article proposes a new phase change memory– (PCM) based memory storage architecture with associated self-adaptive data filtering for various embedded devices to support energy efficiency as well as high computing power. In this approach, PCM-based memory storage can be used as working memory and mass storage layers simultaneously, and a self-adaptive data filtering module composed of small DRAM dual buffers was designed to improve unfavorable PCM features, such as asymmetric read/write access latencies and limited endurance and enhance spatial/temporal localities. In particular, the self-adaptive data filtering algorithm enhances data reusability by screening potentially high reusable data and predicting adequate lifetime of those data depending on current victim time decision value. We also propose the possibility that a small amount of DRAM buffer is embedded into mobile processors, keeping this as small as possible for cost effectiveness and energy efficiency. Experimental results show that by exploiting a small amount of DRAM space for dual buffers and using the self-adaptive filtering algorithm to manage them, the proposed system can reduce execution time by a factor of 1.9 compared to the unified conventional model with same the DRAM capacity and can be considered comparable to 1.5× DRAM capacity.

Locality aware management on NAND flash-based main memory for in-memory database systems

Conventional database systems manage all data on hard disks, but due to a hard disks frequent I/O operations, this kind of management exposes critical problems when data is huge or operations are complex and frequent. As the size of the main memory continues to increase, main memory architecture and management becomes the major research trend in big data processing. Thus, we propose an optimized NAND Flash-based main memory (NFMM) structure for in-memory database systems to achieve the goal of having DRAM like performance at the lower cost and power consumption of Flash memory. For this goal, a horizontal combination of DRAM and NAND Flash memory is designed as a main memory model for database applications. A stream buffer and a DRAM buffer are designed to compensate for the slow access latency of Flash memory. Its optimized management method is designed to enhance the accessing locality and manage the stream buffer by prefetching pages. To evaluate the performance, Redis and Yahoo! Cloud Service Benchmark (YCSB) are used. In our experiment, a stream buffer is used to improve the data transfer speed. The result shows that in the proposed system, the execution time can achieve only 1.16x to 1.21x slower on average. At the same time, optimized NAND Flash-based main memory with 40 entries of stream buffer reduces power consumption up to 25% compared to the DRAM-based main memory system.