Chetan D. Parikh

A new charge-control model for single- and double-heterojunction bipolar transistors

A new charge-control relation is derived for heterojunction bipolar transistors. The relation is valid for arbitrary doping density profiles and for all levels of injection in the base. It is applicable to both single- and double-heterojunction transistors. The model is an improvement over another recently proposed charge-control model that was valid only for constant doping density and low injection in the base. Large- and small-signal equivalent circuit models are also presented for heterojunction bipolar transistors. Comparisons with numerical and experimental data show excellent agreement. >

Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFETs

The influence of channel length and oxide thickness on the hot-carrier induced interface (N/sub it/) and oxide (N/sub ot/) trap profiles is studied in n-channel LDD MOSFETs using a novel charge pumping (CP) technique. The technique directly provides separate N/sub it/ and N/sub ot/ profiles without using simulation, iteration or neutralization, and has better immunity from measurement noise by avoiding numerical differentiation of data. The N/sub it/ and N/sub ot/ profiles obtained under a variety of stress conditions show well-defined trends with the variation in device dimensions. The N/sub it/ generation has been found to be the dominant damage mode for devices having thinner oxides and shorter channel lengths. Both the peak and spread of the N/sub it/ profiles have been found to affect the transconductance degradation, observed over different channel lengths and oxide thicknesses. Results are presented which provide useful insight into the effect of device scaling on the hot-carrier degradation process.

Space-charge region recombination in heterojunction bipolar transistors

A new comprehensive model for space-charge region (SCR) recombination current in abrupt and graded energy gap heterojunction bipolar transistors (HBTs) is derived. It is shown that if a spike is present in one of the bands at the heterojunction interface, the SCR recombination current becomes interrelated with the collector current. A previously proposed charge control model for the HBT is modified to include the SCR recombination current. The model is used to study SCR recombination characteristics in HBTs. >

A comprehensive study of hot-carrier induced interface and oxide trap distributions in MOSFETs using a novel charge pumping technique

A novel simulation-independent charge pumping (CP) technique is employed to accurately determine the spatial distributions of interface (N/sub it/) and oxide (N/sub 0t/) traps in hot-carrier stressed MOSFETs. Direct separation of N/sub it/ and N/sub 0t/ is achieved without using simulation, iteration, or neutralization. Better immunity from measurement noise is achieved by avoiding numerical differentiation of data. The technique is employed to study the temporal buildup of damage profiles for a variety of stress conditions. The nature of the generated damage and trends in its position are qualitatively estimated from the internal electric field distributions obtained from device simulations. The damage distributions are related to the drain current degradation and well-defined trends are observed with the variations in stress biases and stress time. Results are presented which provide fresh insight into the hot-carrier degradation mechanisms.

A direct charge pumping technique for spatial profiling of hot-carrier induced interface and oxide traps in MOSFETs

Abstract A new charge pumping (CP) technique is proposed to obtain the spatial profile of interface-state density ( N it ) and oxide charges ( N ot ) near the drain junction of hot-carrier stressed MOSFETs. Complete separation of N it from N ot is achieved by using a direct noniterative method. The pre-stress CP edge is corrected for the charges associated with both the generated N it and N ot . A closed form model is developed to predict the stress-induced incremental CP current. The damage distributions are obtained after fitting the model with experimental data.

100 nm channel length MNSFETs using a jet vapor deposited ultra-thin silicon nitride gate dielectric

Metal-nitride-semiconductor (MNS) FETs with channel lengths down to 100 nm with a novel jet vapor deposited (JVD) SiN insulator as gate dielectric are fabricated and characterized for their electrical performance. By employing the charge pumping technique, the SiN interface quality and its effect on the transistor performance are evaluated. We show that, compared to conventional SiO/sub 2/ MOSFETs, the SiN devices show lower gate leakage current, competitive drain current drive and transconductance, good interface quality, and reduced hot-carrier degradation.

Analysis of breakdown voltage and on resistance of super junction power MOSFET CoolMOS/sup TM/ using theory of novel voltage sustaining layer

Conventional VDMOS (vertically double diffused metal oxide semiconductor) Technology for power devices was constrained by the Silicon Limit. This is now improved to have a linear relation between on resistance (R/sub on/) and breakdown voltage (BV) instead of the quadratic relation. Theory of novel voltage sustaining layers (SJ-theory) recently published analytically models the super junction drift layers (SJ-drift layer). The authors have designed SJ-layers based on this theory and used to construct the SJ-MOSFET: CoolMOS structure. The claim of the theory that the doping level in the drift layer can now be increased by at least me order of magnitude without lowering BV is analyzed in detail. With the new silicon limit, one now can increase BV of a power device, just by increasing thickness of the SJ-drift layer. R/sub on/ and BV relationship as the thickness of the device varies is analyzed with the help of simulation. The limitations and constraints of applying SJ-theory for the CoolMOS structure are discussed. The SJ- theory does not model the behavior of R/sub on/ and BV for a fixed geometry as doping level changes. The authors observed that for a fixed geometry the rate of reduction of the BV depends on the cell pitch. This rate is large for the higher cell pitch. The effect of charge imbalance created due the channel region in CoolMOS is also investigated.

Performance and hot-carrier reliability of 100 nm channel length jet vapor deposited Si/sub 3/N/sub 4/ MNSFETs

Metal-nitride-semiconductor FETs (MNSFETs) having channel lengths down to 100 mm and a novel jet vapor deposited (JVD) Si/sub 3/N/sub 4/ gate dielectric have been fabricated and characterized. When compared with MOSFETs having a thermal SiO/sub 2/ gate insulator, the MNSFETs show a comparable drain current drive, transconductance, subthreshold slope and pre-stress interface quality. A novel charge pumping technique is employed to characterize the hot-carrier induced interface-trap generation in MNSFETs and MOSFETs. Under identical substrate current during stress, MNSFETs show less interface-state generation and drain current degradation, for various channel lengths, stress times and supply voltages, despite the fact that the Si-Si/sub 3/N/sub 4/ barrier (2.1 eV) is lower than the Si-SiO/sub 2/ barrier (3.1 eV). The time and voltage dependence of hot-carrier degradation has been found to be distinctly different for MNSFETs compared to SiO/sub 2/ MOSFETs.

A compact model for the N-well resistor

Abstract A simple and compact model is derived for the n-well resistor. The model was derived specifically for use in simulation and design of ESD protection circuits using SPICE. Hence it encompasses three regions of resistor operation: linear and velocity saturation, avalanche multiplication and snapback and high injection. Excellent fit with experimental data is found.

A study of 100 nm channel length asymmetric channel MOSFET by using charge pumping

Lateral Asymmetric Channel (LAC) MOSFETs with channel lengths down to 0.1 μm have been fabricated and characterized for their electrical performance. Using charge pumping, we show, for the first time, channel V T profiles obtained experimentally, demonstrating realization of asymmetric channel MOSFETs down to 0.1 μm channel lengths. Our detailed experimental characterizations show improved performance for LAC MOSFETs over conventional MOSFETs, in addition to excellent hot-carrier reliability. Based on 2-D device simulation results, we attribute the improved hot-carrier reliability in LAC MOSFETs to the reduced peak lateral electric field in the channel.