Sudhama C. Shastri

RF Characteristics of a high-performance, 10-fF//spl mu/m/sup 2/ capacitor in a deep trench

We report the properties of a novel polysilicon-insulator-polysilicon trench capacitor with a 380-/spl Aring/ Si/sub 3/N/sub 4/ dielectric that is designed and fabricated for high-frequency bypass and decoupling applications. The capacitor has a specific capacitance as high as 10 fF//spl mu/m/sup 2/ normalized to its footprint area, and a breakdown voltage greater than 15 V at room temperature. The measured S-parameters are in excellent agreement with simulations of an equivalent circuit model that includes a shunt substrate resistance to ground (R/sub sub/). A geometric factor /spl mu/ is defined as the ratio of the imaginary parts of Y/sub 11/ and -Y/sub 21/ at low frequency. The values of /spl mu/ and, consequently, R/sub sub/ are extracted from fitting the measured S-parameter data, and the layout dependence of /spl mu/ and R/sub sub/ is also explained by the model.

Multi-channel, high-density, ultra-low capacitance arrays for ESD and surge protection

A novel protection device providing ultra-low line capacitance and improved ESD (J. E. Vinson et al., 2003) and surge capability is presented. Applications include stand-alone protection arrays and integrated protection in baseband- or RF-filters. A proprietary epitaxial layer and isolation capability enable high levels of surge power handling capability, while keeping line capacitance low and reducing device footprint. The response of the device to ESD and surge stresses is investigated at wafer- and package-level. Process condition variations and derived structures are studied, along with a consideration of issues related to the measurement of capacitance, ESD and surge capability.

Reoxidation of silicon nitride studied using x-ray photoelectron spectroscopy and transmission electron microscopy

The chemical composition of oxynitride films obtained by furnace oxidation of silicon nitride (Si3N4) in a dry or wet oxygen ambient at a substrate temperature of 900–1000 °C is characterized using x-ray photoelectron spectroscopy and cross-sectional transmission electron microscopy. The dependence of the oxidation kinetics on the initial nitride thickness dnit is also investigated in the range of 18–500 A. In the case of dnit=500 A, only the surface of the nitride is oxidized after a 13 min 900 °C oxidation in a wet ambient. In contrast, for dnit=18 and 40 A, under the same conditions condition, the underlying Si substrate is oxidized in addition to Si3N4. Furthermore, it is found that the oxidation rate of 500 A Si3N4 increases by approximately 14%–21% when 2% hydrogen chloride (HCl) is added to the oxidizing ambient. Increases in HCl content beyond 2% do not result in any further enhancement of the oxidation of the nitride film.

A new method for extracting base resistance in bipolar transistors

The base resistance extraction method presented by Linder and coworkers (2001) requires an array of dual-base npn test structures to separate the intrinsic base resistance from its extrinsic counterpart (denoted as R/sub BI/ and R/sub BX/, respectively). This requirement imposes real-estate constraints, especially when the nonproduct silicon area is limited. In contrast, we propose a new technique for R/sub BI/ and R/sub BX/ extraction using only one (rather than multiple) dual-base devices. The physics behind this technique is that current injection swings from one side of the emitter window to the other as a result of a polarity switch of the dc bias difference (/spl Delta/V/sub B/) between the two separate bases. Specifically, as a constant current I/sub E/ is pulled out of the emitter, the emitter voltage (V/sub E/) is monitored as a function of /spl Delta/V/sub B/. A closed-form solution for the partial derivative of V/sub E/ with respect to /spl Delta/V/sub B/ is derived from a physics-based model. The solution predicts that k/sub 1/+k/sub 2/=1 and R/sub BI//R/sub BX/=k/sub 1//k/sub 2/-1, where k/sub 1/ and k/sub 2/ are defined as the asymptotic values of the V/sub E/ versus /spl Delta/V/sub B/ slopes at very high positive and negative /spl Delta/V/sub B/, respectively. A dual-base test structure with an emitter size of 0.4/spl times/4.0 /spl mu/m/sup 2/ is fabricated using a self-aligned, double-poly process, and k/sub 1/=0.85 and k/sub 2/=0.15 are extracted. As a result, we obtain R/sub BI//R/sub BX/=4.67 and an intrinic base sheet resistance of 15.7 k/spl Omega///spl square/.

Extraction of base and emitter series resistances from the net transadmittance parameter

We report a new high-frequency technique for extracting base and emitter resistances (R/sub bb/ and R/sub e/, respectively) of a bipolar junction transistor. We highlight, for the first time, the physical significance of the net transadmittance parameter (y/sub 12/-y/sub 21/) as a figure of merit for the transistors intrinsic performance. We report that while Real(y/sub 12/-y/sub 21/) increases monotonically with frequency, Imag(y/sub 12/-y/sub 21/) exhibits a peak in the GHz range. This peak is attributed to competition between the obstruction of signals as a result of the base-collector capacitance, and the shunt path to ground. We have proven, both theoretically and experimentally, that -1/Real(y/sub 12/-y/sub 21/) is linearly proportional to /spl omega//sup 2/ with a y-intercept of 1/g/sub m/+R/sub e/+R/sub bb///spl beta//sub dc/. By combining this result with the Basaran-Berroth method, individual values of R/sub e/ and R/sub bb/ are extracted and plotted as a function of V/sub be/. Data from transistors with various emitter lengths further validate the efficacy of this extraction technique.