Gary H. Loechelt

UltiMOS: A local charge-balanced trench-based 600V super-junction device

This paper for the first time reports on a novel “local” charge balanced trench-based super junction transistor. The local charge balance is achieved by selectively growing thin highly-doped n-type and p-type layers in a deep trench structure. The final charge-balanced trench structure is finished with an oxide-sealed airgap. Devices rated at 10A with V<inf>bd</inf>=730V and a Ron=23 mΩ.cm² are demonstrated.

RF Characteristics of a high-performance, 10-fF//spl mu/m/sup 2/ capacitor in a deep trench

We report the properties of a novel polysilicon-insulator-polysilicon trench capacitor with a 380-/spl Aring/ Si/sub 3/N/sub 4/ dielectric that is designed and fabricated for high-frequency bypass and decoupling applications. The capacitor has a specific capacitance as high as 10 fF//spl mu/m/sup 2/ normalized to its footprint area, and a breakdown voltage greater than 15 V at room temperature. The measured S-parameters are in excellent agreement with simulations of an equivalent circuit model that includes a shunt substrate resistance to ground (R/sub sub/). A geometric factor /spl mu/ is defined as the ratio of the imaginary parts of Y/sub 11/ and -Y/sub 21/ at low frequency. The values of /spl mu/ and, consequently, R/sub sub/ are extracted from fitting the measured S-parameter data, and the layout dependence of /spl mu/ and R/sub sub/ is also explained by the model.

Body-diode related losses in Shield-Plate FETs for SiP 12V-input DC/DC buck converters operating at high-frequency (4MHz)

The power losses in System-in-Package (SiP) 12V-input DC/DC buck converters with advanced 30V Shield-Plate FETs (SP-FETs) are assessed by experiment and simulation with special interest in the body-diode contribution. Unlike previous work, rise/fall times and on/off deadtimes are in the nanosecond range to provide high efficiency at high frequency operation (1-4MHz).

A high-speed silicon FET for efficient DC-DC power conversion

A novel silicon device architecture for DC-DC power conversion is reported. Efficient switching at high frequencies (1-5 MHz) is achieved by simultaneously reducing gate charge, reverse capacitance, and gate resistance while still maintaining good on-state resistance and off-state breakdown voltage. Power efficiencies in excess of 88% were realized in a synchronous buck converter running at 1.3 MHz.

Process & design impact on BV DSS stability of a shielded gate trench power MOSFET

This paper discusses the breakdown voltage (BVDSS) characteristics of an n-channel charge balanced shielded gate trench power MOSFET. The study emphasizes on elements that affect the BVDSS stability of such devices to gain good control on design and process/device parameters in order to produce a robust product. Breakdown voltage (BVDSS) walk-in or walk-out can be observed when certain process (e.g., epi doping concentration) and design layout (e.g., termination) conditions are not in coherence.

A new method for extracting base resistance in bipolar transistors

The base resistance extraction method presented by Linder and coworkers (2001) requires an array of dual-base npn test structures to separate the intrinsic base resistance from its extrinsic counterpart (denoted as R/sub BI/ and R/sub BX/, respectively). This requirement imposes real-estate constraints, especially when the nonproduct silicon area is limited. In contrast, we propose a new technique for R/sub BI/ and R/sub BX/ extraction using only one (rather than multiple) dual-base devices. The physics behind this technique is that current injection swings from one side of the emitter window to the other as a result of a polarity switch of the dc bias difference (/spl Delta/V/sub B/) between the two separate bases. Specifically, as a constant current I/sub E/ is pulled out of the emitter, the emitter voltage (V/sub E/) is monitored as a function of /spl Delta/V/sub B/. A closed-form solution for the partial derivative of V/sub E/ with respect to /spl Delta/V/sub B/ is derived from a physics-based model. The solution predicts that k/sub 1/+k/sub 2/=1 and R/sub BI//R/sub BX/=k/sub 1//k/sub 2/-1, where k/sub 1/ and k/sub 2/ are defined as the asymptotic values of the V/sub E/ versus /spl Delta/V/sub B/ slopes at very high positive and negative /spl Delta/V/sub B/, respectively. A dual-base test structure with an emitter size of 0.4/spl times/4.0 /spl mu/m/sup 2/ is fabricated using a self-aligned, double-poly process, and k/sub 1/=0.85 and k/sub 2/=0.15 are extracted. As a result, we obtain R/sub BI//R/sub BX/=4.67 and an intrinic base sheet resistance of 15.7 k/spl Omega///spl square/.