Sudhanshu Shekhar Jamuar
Universiti Putra Malaysia
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Publication
Featured researches published by Sudhanshu Shekhar Jamuar.
european conference on circuit theory and design | 2007
Pooria Varahram; Sudhanshu Shekhar Jamuar; Somayeh Mohammady; Mohd Nizar Hamidon; Sabira Khatun
Digital predistortion of a baseband signal is a well-known method of power amplifier (PA) linearization used to reduce adjacent channel interference (ACI) in a non constant envelope modulation system. This paper discusses the application of adaptive digital baseband predistortion linearization to radio frequency (RF) power amplifiers (PAs) that exhibit memory effects. This technique is a highly cost- effective way to linearize Power amplifiers (PAs), but most existing architectures assume that the PA has a memoryless nonlinearity. For wider bandwidth applications such as wideband code-division multiple access (WCDMA) or wideband orthogonal frequency-division multiplexing (W- OFDM), PA memory effects can no longer be ignored. In this paper a new technique for adaptation of digital predistorter that considers memory effects in power amplifiers is proposed. This method is a combination of two techniques, memory polynomial predistortion and slope-dependent method. This new technique is validated by using a 1.9 GHz 60 W LDMOS power amplifier and various signals such as 2- carrier CDMA and 3-carrier CDMA.
Iete Technical Review | 2008
Susheel Sharma; S. S. Rajput; Sudhanshu Shekhar Jamuar
Abstract Floating-gate MOS transistor (FGMOS) has proved to be suitable for low-voltage analog applications, owing to its threshold voltage programmability. This tutorial paper presents FGMOS based circuit structures and their applications in analog signal processing. The FGMOS based current mirror and its application as voltage controlled current source has been presented. The performance of these structures has been verified using PSpice simulations for 0.5 im CMOS technology at 0.75 V.
Measurement Science and Technology | 2007
L. H. Sia; Sudhanshu Shekhar Jamuar; Roslina Mohd Sidek; Mohd Hamiruce Marhaban
This note describes a digital signal processor (DSP) based waveform generator, which can generate a sine wave, up to 24 kHz, a square wave, up to 5 kHz, and a triangular wave, up to 12 kHz. A DSP starter kit with Code Composer Studio has been used in the design of a waveform generator. The waveform generators can also produce periodic arbitrary waveforms and amplitude modulated signals. Two synchronized signals can be obtained by using the waveform generator too. The spectral components of the signals generated are found comparable with a commercially available signal generator. The total harmonic distortion of the sine wave generated is less than 0.6%.
ieee international conference on semiconductor electronics | 2006
Rohan Sehgal; S.S. Rajput; Sudhanshu Shekhar Jamuar
A two-stage low voltage operational amplifier for operation at plusmn0.4 V is proposed. The amplifier incorporates a low voltage current mirror designed using standard floating gate MOSFETs. The proposed op amp possesses a 49 dB open-loop gain, a high bandwidth of 698 kHz, 42deg phase margin and consumes only 28.6 muW. The operation of the proposed current mirror and op amp has been confirmed by PSPICE simulations, using 0.13 mum CMOS technology.
international workshop on antenna technology | 2005
Chee Kyun Ng; Sabira Khatun; Borhanuddin Mohd Ali; Sudhanshu Shekhar Jamuar; Mahamod Ismail
In this paper, we introduce a new duplexing system, the so-called space division duplex, which can eliminate all kinds of interference. This new duplexing system consists of smart antenna multiple steered narrow beams and orthogonal large area synchronous spread spectrum codes. The purpose is to increase system capacity while maintaining its zero correlation window characteristics. The major types of interference and the properties of large area synchronous codes to combat these are studied. An overview of code division duplexing systems applying these orthogonal smart codes in a wireless environment is analyzed. This analysis shows that the number of orthogonal codes which can be utilized is limited. The proposed solution of a space division duplexing system, with its advantages, is presented. In addition, a code reuse concept is proposed to overcome the limitation of orthogonal codes. Finally, the system performance in term of spectral efficiency and capacity are presented.
asia-pacific conference on communications | 2007
Khalid Eltahir Mohamed; Borhanuddin Mohd Ali; Sudhanshu Shekhar Jamuar; Sabira Khatun; Alyani Ismail
It is clear now that it is virtually impossible to adopt or impose on a single standard for all wireless networks. Hence, software defined radio (SDR) technology emerged which addresses this issue. This paper describes the design of CDMA digital transmitter for a multi-standard SDR base band platform. The platform consists of reconfigurable and reprogrammable hardware platform which provide different standards with a common platform. This paper focus also on the methods of generate VHDL model of CDMA transmitter. This model can be implemented with Field Programmable Gate Array (FPGA).
student conference on research and development | 2006
Lini Lee; Roslina Mohd Sidek; Sudhanshu Shekhar Jamuar; Sabira Khatun
This paper presents a dual band low noise amplifier (LNA) for 1.8 GHz DECT and 2.4 GHz WLAN applications employing positive feedback technique. This LNA exploits a positive feedback capacitor connected to a conventional cascaded inductive source degenerated LNA whereby the connection of a capacitor determines the operating frequency of the LNA. For operation at 1.8 GHz DECT, the capacitor is feedback to both transistors of the cascaded LNA and as for 2.4 GHz WLAN application, the capacitor is feedback to only one of the transistors. Two switches are employed to control the connection of the feedback capacitor to the LNA. By switching the connection of the feedback capacitor, the narrow-band gain and impedance matching are achieved at both 1.8 GHz and 2.4 GHz frequency bands. The LNA has been simulated using 0.18 mum CMOS technology and results attained for both two bands are as followed; gain, S21=21 dB, noise figure, NF=0.8 dB and linearity with third-order intercept point, IIP3=-0.13 dBm. Simulation results prove that the technique works and a dual-band LNA with a chip size comparable to a single-band LNA is realized with the proposed topology.
asia-pacific conference on communications | 2005
Chee Kyun Ng; Mahamod Ismail; Borhanuddin Mohd Ali; Sabira Khatun; Sudhanshu Shekhar Jamuar
Spatial filtering using smart antenna has emerged as a promising technique to improve the performance of cellular systems. Cell splitting and sectorisation in CDMA systems could result in an increase in system capacity. In this paper, we investigate the impact of inter-cell interference on reverse link capacity in a joint multiple access system arising from the combination of CDMA and SDMA systems. The system capacity of CDMA and SDMA systems is reviewed individually. The co-channel and antenna side-lobes interferences in SDMA systems due to the randomly located mobile users in a non-uniform traffic cell are studied. Therefore, the most realistic reverse link capacity improvement of the joint multiple access system is presented here by taking into consideration both intra-sector and inter-sector interferences. The results are based on the system parameters of CDMA and SDMA systems
international rf and microwave conference | 2006
Lini Lee; Sudhanshu Shekhar Jamuar; R. Mohd Sidek; Sabira Khatun
A low voltage topology that uses a capacitively coupled resonating element has been introduced using 0.18 mum CMOS technology. The topology utilizes the decoupling scheme to dc isolate circuit elements that are connected in series and share a common dc current. A 5.7 GHz variable-gain low noise amplifier (VGLNA) is presented with simulation results exhibiting a noise figure of 1.02 dB, power gain of 19.41 dB with gain tuning range of 6 dB and IIP3 of -1.11 dBm. The power consumption reported is 12.88 mW at supply of Vdd = 0.7 V for power optimization circuit. Simulation results show that the proposed VGLNA has better noise performance and improved power consumption compared to the conventional cascode VGLNA
ieee region 10 conference | 2005
Borhanuddin Mohd Ali; Sudhanshu Shekhar Jamuar; Mahamod Ismail
In sphere decoding the choice of sphere radius is crucial to excellent performance. In Chan-Lee sphere decoding - based algorithm, the problem of choosing initial radius has been solved by making the radius sufficiently large, thus increasing the size of the search region. In this paper we present maximum likelihood decoding using simplified sphere decoder as apposed to the original sphere decoder for the detection of cubic structure quadrature amplitude modulation symbols. This simple algorithm based on Chan-Lee sphere decoder allows the search for closest lattice point in a reduced complexity manner compared to original sphere decoder for multiple input multiple output system with perfect channel state information at the receiver. Results show symbol error rate has stabilized even at very low initial value of the square radius.