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Dive into the research topics where Sudip Kundu is active.

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Featured researches published by Sudip Kundu.


international conference on nanotechnology | 2008

A Strategic Review of Recent Progress in Metamorphic Quantum Well Based Heterostructure Electronic Devices

Partha Mukhopadhyay; Palash Das; Saptarshi Pathak; Sudip Kundu; Edward Y. Chang; Dhrubes Biswas

Recent expansion in the demand for high performance applications require high performance devices. It can be achieved by utilizing features of the quantum well based heterostructures on metamorphic buffer. Based on this metamorphic technique two electronic devices, named high electron mobility transistors (MHEMTs) & heterojunction bipolar transistors (MHBTs) are the areas of interest now-a-days. This paper reviews the remarkable progress being made in the development of InP based MHEMT & MHBT in the context of material properties, device structures, DC and RF performances for the development of low cost, high performance power amplifier (PA) and low noise amplifier (LNA) with high linearity applications.


Archive | 2018

Tunable Universal Filter in ±0.5 V 32 nm CNFET for ISM 2.4 GHz Bluetooth/Zigbee Transceivers

Jyoti Sharma; Mohd. Samar Ansari; Sudip Kundu

Carbon nanotube field-effect transistors (CNFETs) have emerged as practicable replacements to conventional MOSFETs for contemporary analog/digital design. This work highlights a current-mode tunable universal filter (CMUF), which can provide band-reject, low-, band-, and high-pass filtering functions, by making use of a new CNFET-based second-generation current-controlled conveyor (CCCII) and grounded capacitors only. The circuit operates on lower power supply and bias currents, and uses smaller capacitors as compared to CMOS counterparts. Corner frequencies (for LPF and HPF) and center frequency (for BPF) have been obtained in the GHz range. Tunability of filter outputs with respect to bias current has been demonstrated. This CMUF is suitable for operation in 868–915 MHz, and 2.4–5 GHz bands used by Zigbee and Bluetooth, respectively. Noise and Monte Carlo analyses have also been performed. The performance of both the CCCII and the CMUF is verified with extensive SPICE simulations.


2017 Devices for Integrated Circuit (DevIC) | 2017

Analysis of AlGaN/GaN high electron mobility transistor for high frequency application

Subrangshu Chatterjee; Anumita Sengupta; Sudip Kundu; Aminul Islam

This paper presents an AlGaN/GaN High Electron Mobility Transistor (HEMT) structure with SiNx surface passivation layer. A T-shaped gate is formed at the top of GaN cap layer. The structure is simulated with Sapphire substrate. Output characteristics curve (Id-Ids), threshold voltage (FT), subthreshold slope and unity current gain cut off frequency (fr) of the device are observed. The proposed device exhibits a threshold voltage Vt= −4 V, peak current is about 500 mA, subthreshold slope of 185 mV/dec and unity current gain cutoff frequency fT= 73.6 GHz. All the simulations are performed using Silvaco ATLASTM.


2017 Devices for Integrated Circuit (DevIC) | 2017

MEMS piezoelectric energy harvester to power wireless sensor nodes for machine monitoring application

Dipta Chaudhuri; Sudip Kundu

Piezoelectric vibration energy harvesters find an important application in powering the wireless sensor nodes used to monitor the condition, wear and tear of AC machines which vibrate at twice the line frequency i.e., 100 Hz. The challenge in the design is to make the resonant frequency of the energy harvester equal to 100 Hz keeping the size less and to obtain the maximum possible output voltage. In this paper various geometries of cantilever beams of a constant length 5 mm have been investigated to get significant reduction in the resonant frequency and to achieve nearly 100 Hz. A new Perforated Tapered shaped cantilever beam has been proposed. The achieved resonant frequency of the final proposed perforated Tapered structure with proof mass is 101 Hz, which is 27.5% lower than that of the commonly used rectangular structure with proof mass of same dimensions. The peak voltage output of the proposed structure is 7.5 V. The proposed structure can be used to generate voltage from the vibration of the AC machines and can provide a long-life solution to the need of powering the batteries in wireless sensor nodes.


international conference on recent advances in information technology | 2016

Investigation on electrical characteristics of FDSOI device for ultra-low power operation

Manisha Guduri; Sudip Kundu; Aminul Islam

This paper aims at modeling of Fully Depleted Silicon on Insulator (FDSOI) device. This work also investigates electrical characteristics like threshold voltage and subthreshold slope of the FDSOI device. The device is modeled using Silvaco Atlas 2-D numerical simulator and the electrical characteristics are simulated using the same. It is seen that the threshold voltage and subthreshold slope of the modeled device is 0.1 V and 79 mV/decade respectively. The results show that the modeled device (FDSOI) exhibits excellent characteristics. It also states that the FDSOI device is worthwhile for ultralow power operation. This device finds its aptness in Internet of Things (IoT) technology.


international conference on nanotechnology | 2010

Reduction of negative differential conductivity effect of AlGaN/GaN HEMTs using gate scaling

Sudip Kundu; Palash Das; Saptarshi Pathak; Partha Mukhopadhyay; Jasvardhan Reddy; Edward Y. Chang; Dhrubes Biswas

Gate characteristic is one of the most important parts for the HEMTs. In this paper the DC and RF performance improvement using gate length scaling has been presented. The results show that reduction of the gate length from 1 µm to 0.15 µm, the current gain cutoff frequency increases from 12 GHz to 56 GHz and power gain cutoff frequency increases from 20.5 GHz to 63 GHz respectively. In this paper we report the first ever simulation based device structure design for reduction of Negative Differential Conductivity (NDC) effect in AlGaN/GaN HEMTs by gate length scaling.


Integration | 2014

ISGP: Iterative sequential geometric programming for precise and robust CMOS analog circuit sizing

Sudip Kundu; Pradip Mandal


Microsystem Technologies-micro-and Nanosystems-information Storage and Processing Systems | 2018

Design and analysis of MEMS based piezoelectric energy harvester for machine monitoring application

Dipta Chaudhuri; Sudip Kundu; Neela Chattoraj


Analog Integrated Circuits and Signal Processing | 2018

An efficient method of Pareto-optimal front generation for analog circuits

Sudip Kundu; Pradip Mandal


Analog Integrated Circuits and Signal Processing | 2018

Modeling and sizing of non-linear CMOS analog circuits used in mixed signal systems

Sudip Kundu; Siddhartha Sarkar; Pradip Mandal; Aminul Islam

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Pradip Mandal

Indian Institute of Technology Kharagpur

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Aminul Islam

Birla Institute of Technology

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Dipta Chaudhuri

Birla Institute of Technology

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Dhrubes Biswas

Indian Institute of Technology Kharagpur

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Neela Chattoraj

Birla Institute of Technology

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Palash Das

Indian Institute of Technology Kharagpur

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Partha Mukhopadhyay

Indian Institute of Technology Kharagpur

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Saptarshi Pathak

Indian Institute of Technology Kharagpur

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Edward Y. Chang

National Chiao Tung University

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Anumita Sengupta

Birla Institute of Technology and Science

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