Pradip Mandal

CMOS op-amp sizing using a geometric programming formulation

The problem of CMOS op-amp circuit sizing is addressed here. Given a circuit and its performance specifications, the goal is to automatically determine the device sizes in order to meet the given performance specifications while minimizing a cost function, such as a weighted sum of the active area and power dissipation. The approach is based on the observation that the first order behavior of a MOS transistor in the saturation region is such that the cost and the constraint functions for this optimization problem can be modeled as posynomial in the design variables. The problem is then solved efficiently as a convex optimization problem. Second order effects are then handled by formulating the problem as one of solving a sequence of convex programs. Numerical experiments show that the solutions to the sequence of convex programs converge to the same design point for widely varying initial guesses. This strongly suggests that the approach is capable of determining the globally optimal solution to the problem. Accuracy of performance prediction in the sizing program (implemented in MATLAB) is maintained by using a newly proposed MOS transistor model and verified against detailed SPICE simulation.

A self-biased high performance folded cascode CMOS op-amp

Cascode CMOS op-amps use a large number of external bias voltages. This results in numerous drawbacks, namely, an area and power overhead, susceptibility of the bias lines to noise and cross-talk and high sensitivity of the bias point to process variations. In this paper we present a self-biasing technique for folded cascode CMOS op-amps that uses no additional devices and no bias voltages other than the two supply rails. The resulting self-biased op-amps are free from the above mentioned drawbacks and exhibit the same performance as existing folded casode op amps, except for a small reduction in slew rate. This is achieved by following transistor sizing constraints derived through detailed circuit analysis. The technique is applied to an existing high performance op amp. Simulation results show that the high performance is maintained while nine bias voltages are eliminated.

A Low Voltage, Low Ripple, on Chip, Dual Switch-Capacitor Based Hybrid DC-DC Converter

Here we propose a low voltage low ripple dual switch- capacitor based hybrid DC-DC converter which is suitable for high dropout embedded regulation. In the proposed topology, along with a linear regulator two switching capacitors are used to store and recycle the charge for better power efficiency. The linear regulator is used to reduce the amount of output voltage ripple that comes from the switching capacitors. The output ripple noise is further reduced by introducing a synthesized counter ripple through the linear regulator. With this noise reduction technique, for an acceptable output ripple noise, the switching capacitors are reduced to a value which can be implemented on chip. The proposed converter circuit is designed in 0.18 mu process for 3.3 V to 1.25 V conversion. With two switching capacitors of 150 pF each, for 10 mA load current and 50 pF load capacitor, peak-peak output voltage ripple is only 45 mV and the achieved power efficiency is 64%.

Low power LVDS transmitter with low common mode variation for 1GB/s-per pin operation

This paper presents the design of a low voltage differential signalling (LVDS) transmitter intended using a LCD panel interface and is capable of transmitting 1GB/s per pin data rate. The transmitter is fully LVDS standard compatible which is achieved by employing a common mode feedback circuit to meet all Ac and DC specifications over PVT variation, specifically due to the implementation of feedback circuit, the common mode variation is made very less quiescent current of 5.5mA. Further, the implementation incorporates the idea of sharing of bias blocks among different transmitters in full chip resulting in less active area. The transmitter is implemented in 3.3V, 0.35/spl mu/ CMOS technology. In this implementation the active area (excluding ESD) per transmitter is 0.039 mm square. The initial silicon data (output offset voltage of 1.20V and differential voltage of 320mV) at room temperature shows the consistency of the simulation results.

A High Performance Switched Capacitor-Based DC-DC Buck Converter Suitable for Embedded Power Management Applications

Here, we propose high performance buck converter architecture suitable for embedded applications. The proposed converter has high power efficiency, high power density, good driving capability, low output ripple, and good line and load regulation. The step down converter is constructed using a simple building block called cross coupled converter. As this block use low swing internal signals to control half of its switches, the required switching loss decreases and these internal control signals enable us to use thin oxide transistor for making switch smaller and reducing power further. In addition, converter uses all the good features of non-overlapping rotational interleaving switching scheme. Switching frequency of the converter is dynamically adjusted based on load current to maintain high power efficiency. Good transient performance is achieved by using dynamic leaker circuit with a marginal increase of static current. The converter is designed in 0.18- m CMOS process to get regulated 1.3-1.6 V output from 3.3 V input supply while output ripple is below 42 mV and provides 86% peak power. For 75% power efficiency, power density of the converter is 0.43 W/mm2 using total 490 pF capacitor.

An Improvised MOS Transistor Model Suitable for Geometric Program Based Analog Circuit Sizing in Sub-micron Technology

This paper presents ways to improve accuracy of performance prediction for geometric program based analog design in submicron regime. Geometric program requires a special monomial form of the device model it uses. The major sources of inaccuracy in this basic model have been identified and it has been shown that slightly relaxing the strict monomial form in order to include second order effects can greatly improve the accuracy. In order to make use of this model we deploy it in collaboration with an iterative solution betterment scheme, by solving the sizing problem as a sequence of geometric programs instead of a single one. We illustrate the efficacy of our scheme through a folded-cascode op-amp sizing example.

An automated design approach for CMOS LDO regulators

This paper presents a method for optimal sizing of CMOS low drop out regulator circuits. The technique relies on the observation that many of the performance metrics of a LDO regulator can be approximated as posynomial functions of design variables. This allows the design problem to be cast as a geometric program. Geometric program is particularly attractive as the tool for optimization as --1)it can be solved very efficiently, 2)it always finds the global minima, 3)infeasible specifications are readily determined and 4)the final solution is completely independent of the initial guess. As a result CMOS LDOs may be conveniently synthesized; moreover the optimal trade off curves between the competing performance metrics, can be obtained very fast.

Automatic generation of saturation constraints and performance expressions for geometric programming based analog circuit sizing

This paper presents a new approach for generating saturation constraints and DC performance expressions for analog integrated circuits. It also proposes a generalized method to develop AC performance expressions of the same in posynomial form. The developed posynomial expressions can be used for well established geometric programming (GP) based sizing optimization. The equation generation method takes very less time and does not require any manual intervention. The proposed method for AC performance expression generation is built on two levels of abstraction of a circuit. At the higher level, referred as macromodel, circuit performance metrics are modeled as function of device parameters such as transconductance (gm), drain conductance (gd), small-signal parasitic capacitances and overdrive voltage (Vov). Whereas, at lower level of the abstraction the device parameters are monomial functions of device sizes and their biases. The two-level abstraction helps to develop technology independent performance model of a circuit. Whereas, the technology dependency is captured through device models. The proposed methods are applied to two well-known CMOS op-amp topologies namely, two-stage and folded-cascode to generate saturation constraints, DC and AC performance expressions. With the developed constraints, both the circuits are designed through GP based circuit optimization in a 0.18 μm UMC technology. Performances of both are verified at their final design points.

Low-power LVDS receiver for 1.3Gbps physical layer (PHY) interface

This paper presents the design of a low voltage differential signaling (LVDS) receiver for a 1.3 Gb/s physical layer (PRY) interface. The receiver supports a wide input common mode range of 0.05 V to 2.35 V and a minimum input differential signal of 100 mV as specified by the IEEE LVDS standard. The design is implemented in 0.13 /spl mu/m CMOS technology using both thick (3.3 V) and thin (1.2 V) gate oxide devices and the receiver consumes 11 mW of power. The receiver provides the interface between PHY and media access control (MAC) sub-layers.

A CMOS beta multiplier voltage reference with improved temperature performance and silicon tunability

A new implementation has been proposed for the beta multiplier voltage reference to improve its performance with regard to process variations. The scope for silicon tunability on the proposed circuit is also discussed. The circuit was implemented in a 0.18 /spl mu/ process and was found to have a temperature sensitivity of less than 500 ppm/C in the virgin die without trimming.