Sudip Shekhar

A capacitor cross-coupled common-gate low-noise amplifier

The conventional common-gate low-noise amplifier (CGLNA) exhibits a relatively high noise figure (NF) at low operating frequencies relative to the MOSFET f/sub T/, which has limited its adoption notwithstanding its superior linearity, input matching, and stability compared to the inductively degenerated common-source LNA (CSLNA). A capacitor cross-coupled g/sub m/-boosting scheme is described that improves the NF and retains the advantages of the CGLNA topology. The technique also enables a significant reduction in current consumption. A fully integrated capacitor cross-coupled CGLNA implemented in 180-nm CMOS validates the g/sub m/-boosting technique. It achieves a measured NF of 3.0 dB at 6.0 GHz and consumes only 3.6 mA from 1.8 V; the measured input-referred third-order intercept ( IIP3) value is 11.4 dBm. The capacitor cross-coupled g/sub m/-boosted CGLNA is attractive for low-power fully integrated applications in fine-line CMOS technologies.

G/sub m/-boosted common-gate LNA and differential colpitts VCO/QVCO in 0.18-/spl mu/m CMOS

The demand for radio frequency (RF) integrated circuits with reduced power consumption is growing owing to the trend toward system-on-a-chip (SoC) implementations in deep-sub-micron CMOS technologies. The concomitant need for high performance imposes additional challenges for circuit designers. In this paper, a g/sub m/-boosted common-gate low-noise amplifier (CGLNA), differential Colpitts voltage-controlled oscillators (VCO), and a quadrature Colpitts voltage-controlled oscillator (QVCO) are presented as alternatives to the conventional common-source LNA and cross-coupled VCO/QVCO topologies. Specifically, a g/sub m/-boosted common-gate LNA loosens the link between noise factor (i.e., noise match) and input matching (i.e., power match ); consequently, both noise factor and bias current are simultaneously reduced. A transformer-coupled CGLNA is described. Suggested by the functional and topological similarities between amplifiers and oscillators, differential Colpitts VCO and QVCO circuits are presented that relax the start-up requirements and improve both close-in and far-out phase noise compared to conventional Colpitts configurations. Experimental results from a 0.18-/spl mu/m CMOS process validate the g/sub m/-boosting design principle.

Design considerations for CMOS low-noise amplifiers

A low-noise amplifier is the first active stage of a CMOS RF receiver. The inductively degenerated common-source LNA (CS-LNA) topology is currently popular because it achieves high gain, low noise figure, etc. The amplifiers performance is reviewed and the optimum Q value that gives the minimum noise figure is derived. It is then compared to the conventional common-gate LNA (CG-LNA) in terms of gain, noise figure, input matching, reverse isolation and stability. Finally, a general g/sub m/-boosted design technique for common-gate RF circuits is introduced that provides lower noise figure and power consumption than the conventional CS-LNA and CG-LNA stages; it also preserves the CG-LNA insensitivity to parasitic input capacitances. In view of CMOS scaling, the CG-LNA topology is attractive for future higher frequency and/or lower power designs.

A 47

A 47 × 10 Gb/s chip-to-chip interface consuming 660 mW is demonstrated in 45 nm CMOS. The circuitry and interconnect are co-designed to minimize power and area for a wide parallel interface. Power is reduced by amortizing clocking, minimizing the span of clock signals and pairing a low-swing transmitter driver with a sensitive receiver sampler. The active silicon area is compressed by 64% relative to the C4 bumps using on-chip transmission line routing. A dense, top-side package connector and bridge enable both high off-chip interconnect density and low overall power by reducing equalization and deskew requirements. The interface also demonstrates fast power management for the I/O circuits. The receiver power can be reduced by 93% during standby and an integrated wake-up timer indicates that all lanes return reliably to active mode in <;5 ns. The interface operates at 470 Gb/s with an aggregate bit error ratio better than 2 ×10-18 while consuming 1.4 mW/Gb/s and occupies 3.2 mm2 active silicon area.

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A general model for injection-locked LC oscillators (LC-ILOs) is presented that is valid for any tank quality factor and injection strength. Important properties of an ILO such as lock-range, phase shift, bandwidth and response to input jitter are described. An LC-ILO together with a half-rate data sampler is implemented as a forwarded-clock I/O receiver in 45-nm CMOS. A strongly-injected low-Q LC oscillator enables clock deskew across 1UI and rejects high-frequency clock jitter. The complete 27 Gb/s ILO-based data receiver has an overall power efficiency of 1.6 mW/Gb/s.

10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS

This paper describes a method for both filtering and deskewing a link clock using a differential injection-locked LC-DCO and demonstrates a forwarded-clock data receiver using this technique operating at 27 Gb/s.

Strong Injection Locking in Low-

We demonstrate that n-doped resistive heaters in silicon waveguides show photoconductive effects with high responsivities. These photoconductive heaters, integrated into microring resonator (MRR)-based filters, were used to automatically tune and stabilize the filters resonance wavelength to the input lasers wavelength. This is achieved without requiring dedicated defect implantations, additional material depositions, dedicated photodetectors, or optical power tap-outs. Automatic wavelength stabilization of first-order MRR and second-order series-coupled MRR filters is experimentally demonstrated. Open eye diagrams were obtained for data transmission at 12.5 Gb/s while the temperature was varied by 5 °C at a rate of 0.28 °C/s. We theoretically show that series-coupled MRR-based filters of any order can be automatically tuned by using photoconductive heaters to monitor the light intensity in each MRR, and sequentially aligning the resonance of each MRR to the lasers wavelength.

Q

A tuned-input tuned-output (TITO) VCO utilizes two resonant-tanks to achieve a low measured phase noise of 130.5 dBc/Hz @ 1 MHz offset from 2.5 GHz center frequency. Improvement in phase noise is achieved with comparable power consumption and tuning range compared to a cross-coupled VCO topology. A TITO cell similar to that in the VCO is used as a common-source amplifier in a current-reuse configuration cascaded with a -boosted common-gate amplifier to realize a high gain (20 dB), low power (2.7 mW) LNA. A technique to improve the linearity of the current-reuse LNA is also presented.

LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver

A fully-integrated common-gate UWB LNA employs a stagger-compensated series peaking technique to extend bandwidth, and a capacitor cross-coupled gm-boosting technique to reduce NF and power. A simple input matching scheme obviates the use of multiple inductors and complex filters. For two versions in 0.18 mum CMOS, BW extension factors are 4.1times and 4.9times, -3dB bandwidths are 1.3-10.7 GHz and 1.3-12.3 GHz, NF are 4.4 dB and 4.6 dB, peak S21 are 8.5 dB and 8.2 dB, and peak IIP3 are 8.3 dBm and 9.1 dBm, respectively. Each differential LNA draws 2.5 mA from 1.8 V

A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in 45nm CMOS

High-speed CMOS microprocessor I/O has scaled aggressively over the past decade in terms of power and performance largely due to advances in equalization and clocking techniques. With future multi-core processors expected to require ≫1TB/s bandwidth and dramatically improved power efficiency, there has been some question as to whether electrical I/O will continue to satisfy chip-to-chip communication requirements over the next decade. In this paper, we show that electrical signaling has the power, performance, and density scaling potential to enable the next several generations of systems and applications. Circuit innovation is aggressively pushing link power efficiency toward 1–2mW/Gb/s while departures from legacy channels to include new topologies and materials can significantly improve the power/performance/density tradeoff. Statistical link-level design tools that allow designers to rapidly quantify high-level architecture tradeoffs will enable balanced link designs that co-optimize power, performance, and channel topology.