Suguru Saito

Mechanism of Plasma-Less Gaseous Etching Process for Damaged Oxides from the Ion Implantation Process

Recently, plasma-less gaseous etching processes have attracted attention for their interesting etching properties. Previously, we reported on the etching properties of theses processes for various kinds of oxides and revealed that they reduce the etch rate of the chemical-vapor-deposited (CVD) oxides more than the conventional wet etching process does [1]. Our results also revealed that depressions called divots in the CVD oxide of the shallow trench isolation (STI) became smaller in size by substituting a plasma-less gaseous etching process for the conventional wet etching process. In semiconductor manufacturing, many processes are used to remove oxides damaged during ion implantation or reactive ion etching on the device surface. Therefore, it is very important to understand the etching properties of plasma-less gaseous etching processes for damaged oxides as well as those for other kinds of oxides. In this report, we evaluate the etching properties of one particular plasma-less gaseous etching process for oxide films damaged during the ion implantation process under various conditions and discuss the mechanism of interesting etching properties for the damaged oxides.

IR sensitivity enhancement of CMOS Image Sensor with diffractive light trapping pixels

We report on the IR sensitivity enhancement of back-illuminated CMOS Image Sensor (BI-CIS) with 2-dimensional diffractive inverted pyramid array structure (IPA) on crystalline silicon (c-Si) and deep trench isolation (DTI). FDTD simulations of semi-infinite thick c-Si having 2D IPAs on its surface whose pitches over 400 nm shows more than 30% improvement of light absorption at λ = 850 nm and the maximum enhancement of 43% with the 540 nm pitch at the wavelength is confirmed. A prototype BI-CIS sample with pixel size of 1.2 μm square containing 400 nm pitch IPAs shows 80% sensitivity enhancement at λ = 850 nm compared to the reference sample with flat surface. This is due to diffraction with the IPA and total reflection at the pixel boundary. The NIR images taken by the demo camera equip with a C-mount lens show 75% sensitivity enhancement in the λ = 700–1200 nm wavelength range with negligible spatial resolution degradation. Light trapping CIS pixel technology promises to improve NIR sensitivity and appears to be applicable to many different image sensor applications including security camera, personal authentication, and range finding Time-of-Flight camera with IR illuminations.

Impact of Electrostatic Effects on Wet Etching Phenomenon in Nanoscale Region

The microminiaturization of semiconductor devices has made it necessary to control the wet etching process on the nanometer order. It is therefore extremely important to understand wet etching reactions in the nanoscale region of solid-liquid interfaces, in order to assist in optimizing process conditions to satisfy the severe demand for semiconductor devices. Simulations performed to analyze the behavior of liquid molecules in the nanoscale region have been reported [1], but there have been few reports of detailed experimental results. We here report detailed experimental results on the wet etching behavior of SiO2 film in the nanoscale region between Si materials.

Behavior Analysis of Si Etching Process with HF/HNO3 Mixture in Single-Spin Wafer Process

The HF/HNO3 mixture Si etching process is widely used to remove stress and damaged layers after Si wafer back grinding. Although there have been many reports on the dip process, there have been few detailed reports on the single-spin process. In a single spin process, Si etch rate distributions largely differ with different HF/HNO3 concentrations. On the other hand, thermal SiO2 etch rate distributions are similar even with different HF/HNO3 concentrations. In this work, we analyzed Si surfaces with XPS (X-ray Photoelectron Spectroscopy) after processing various HF/HNO3 mixture concentrations. SiOx stays steady in any wafer position and HNO3 concentration, whereas SiO2 thickens depending on HNO3 concentration at the center. We assumed that Si etch rate distributions were caused by HF or HNO3 consumption and confirmed this assumption was correct in a wafer center SiN cover experiment.

Effect of WET treatment on Group III-V Compound Semiconductor Surface

In this work, we investigated interfacial properties of InP, which is a typical group III-V compound used for semiconductors, by using a chemical-treated metal oxide semiconductor (MOS) capacitor. The interfacial properties of InP is more affected by interface state density than the surface roughness and is greatly affected by In2O3 in particular. Additionally, we evaluated In2O3 growth during 24-hour rinsing and air exposure and found that In2O3 on an InP surface grows larger during rinsing than during air exposure. To reduce In2O3, the rinse needs to be optimized.

Analysis of Si Wet Etching Effect on Wafer Edge

We investigated the effect of Si wet etching on the vertical step at wafer edge. We found that the concave-convex shape appeared at the wafer edge after Si etching by the Atomic Force Microscopy analysis. From the liquid simulation and the detailed evaluation of Si etching rate, we revealed that the concave-convex shape was formed by the distribution of the fluid velocity at the wafer edge.

Evaluation of Hafnium Contamination on Wafer Surfaces after the Wet Cleaning Process

High-k gate dielectrics and metal gate electrodes have become essential for emerging device technologies because they enable the continuous scaling down of devices while maintaining a high performance [. However, since they are composed of novel metallic elements that have never before been used in conventional processes, special care must be taken when handling these materials in the production line. In particular, cross-contamination that occurs due to transporting contamination via processed wafers can cause serious problems such as deterioration of device properties and yield loss [. The process of cleaning the backside and bevel of a wafer is now increasingly important for avoiding these problems. To date, there has been no detailed evaluation of contamination removal on various films performed for elements such as hafnium, which is one of the key elements in high-k/metal gate technologies. In this study, we evaluated hafnium contamination on three types of wafer surface after the cleaning process and investigated the cause of different residual amounts of hafnium contamination on the different wafers.