Takayuki Toshima

Contact hole shrink process using graphoepitaxial directed self-assembly lithography

Abstract. A contact hole shrink process using directed self-assembly lithography (DSAL) for sub-30 nm contact hole patterning is reported on. DSAL using graphoepitaxy and poly (styrene-block-methyl methacrylate) (PS-b-PMMA) a block copolymer (BCP) was demonstrated and characteristics of our process are spin-on-carbon prepattern and wet development. Feasibility of DSAL for semiconductor device manufacturing was investigated in terms of DSAL process window. Wet development process was optimized first; then critical dimension (CD) tolerance of prepattern was evaluated from three different aspects, which are DSA hole CD, contact edge roughness (CER), and hole open yield. Within 70+/−5  nm hole prepattern CD, 99.3% hole open yield was obtained and CD tolerance was 10 nm. Matching between polymer size and prepattern size is critical, because thick PS residual layer appears at the hole bottom when the prepattern holes are too small or too large and results in missing holes after pattern transfer. We verified the DSAL process on a 300-mm wafer at target prepattern CD and succeeded in patterning sub-30 nm holes on center, middle, and edge of wafer. Average prepattern CD of 72 nm could be shrunk uniformly to DSA hole pattern of 28.5 nm. By the DSAL process, CD uniformity was greatly improved from 7.6 to 1.4 nm, and CER was also improved from 3.9 to 0.73 nm. Those values represent typical DSAL rectification characteristics and are significant for semiconductor manufacturing. It is clearly demonstrated that the contact hole shrink using DSAL is a promising patterning method for next-generation lithography.

Novel photoresist stripping technology using ozone/vaporized water mixture

The authors have developed a new process as an alternative to sulfuric peroxide mixture (SPM) cleaning of Si wafers. This process, vapor ozone strip (VOS), uses ozone and vaporized water, significantly reducing any effect on environment, health and safety. The process is more effective than ozone water immersion, because high concentration ozone gas and high temperature water can be used simultaneously. Also, the process uses the highly reactive OH* radical species. The VOS process is able to strip photoresist at a higher rate than other techniques using ozone. Ion implanted photoresist and etched photoresist can be stripped. VOS has demonstrated equivalent performance to SPM in electrical reliability testing.

Contact hole shrink process using directed self-assembly

We report on a contact hole shrink process using directed self-assembly. A diblock copolymer, poly (styrene-blockmethyl methacrylate) (PS-b-PMMA), is used to shrink contact holes. Contact hole guide patterns for graphoepitaxy are formed by ArF photoresists. Cylindrical domains of PMMA is removed using organic solvents after DUV (λ <200 nm) irradiation. In this work, it is found that a solvent system is the best developer from the evaluated single solvent systems and mixed solvent systems. The wet development of PS-b-PMMA strongly depends on total exposure dose of DUV irradiation. With lower exposure dose, the cylindrical domains of PMMA are not clearly removed. With optimum exposure dose, PMMA is developed clearly. The contact hole guide patterns of 75 nm in diameter are successfully shrunk to 20 nm in diameter using the wet development process.

Influence of the watermark in immersion lithography process

In the liquid immersion lithography, uses of the cover material (C/M) films were discussed to reduce elution of resist components to fluid. With fluctuation of exposure tool or resist process, it is possible to remain of waterdrop on the wafer and watermark (W/M) will be made. The investigation of influence of the W/M on resist patterns, formation process of W/M, and reduction of pattern defect due to W/M will be discussed. Resist patterns within and around the intentionally made W/M were observed in three cases, which were without C/M, TOK TSP-3A and alkali-soluble C/M. In all C/M cases, pattern defect were T-topped shapes. Reduction of pattern defects due to waterdrop was examined. It was found that remained waterdrop made defect. It should be required to remove waterdrop before drying, and/or to remove the defect due to waterdrop. But new dry technique and/or unit will be need for making no W/M. It was examined that the observation of waterdrop through the drying step and simulative reproduction of experiment in order to understand the formation mechanism of W/M. If maximum drying time of waterdrop using immersion exposure tool is estimated 90 seconds, the watermark of which volume and diameter are less than 0.02 uL and 350um will be dried and will make pattern defect. The threshold will be large with wafer speed become faster. From result and speculations in this work, it is considered that it will be difficult to development C/M as single film, which makes no pattern defects due to remained waterdrop.

Electro-less barrier/seed formation in high aspect ratio via

This paper reports on the results of applying an electroless (Eless) plating technique to the deposition of barrier and seed layers in high aspect ratio through-silicon vias (TSVs) and its potential for reducing costs, improving performance, and raising productivity in 3D Integration. The newly developed technology is applicable not only to barrier/seed deposition on TEOS insulation film but also to the uniform deposition of a seed layer on conventional vacuum-deposited barrier layers (such as PVD-Ta). The application of Eless technology can also reduce the occurrence of voids at the bottom of vias that easily occur in Cu electroplating, even when using thin-film seed layers (under 100 nm), which means that improved productivity and reduced process costs can also be expected.

Nanopatterning of diblock copolymer directed self-assembly lithography with wet development

We report wet development technique for directed self-assembly lithography pattern. For typical diblock copolymer, poly (styrene-block-methyl methacrylate) (PS-b-PMMA), the PMMA area is removed by O2 plasma. However, O2 plasma attack also etches off PS area simultaneously. As a result, the thickness of residual PS pattern is thinner and it causes degradation of PS mask performance. PS thickness loss in the device integration is not desirable as etching mask role. In this work, we applied wet development technique which could be higher selectivity to keep PS film thickness after pattern formation. Especially, we propose the method using low pressure mercury lamp and conventional TMAH (2.38%) as developer. It is expected to accomplish pattern formation in one track with coating, baking, exposure and development.

Impact of Electrostatic Effects on Wet Etching Phenomenon in Nanoscale Region

The microminiaturization of semiconductor devices has made it necessary to control the wet etching process on the nanometer order. It is therefore extremely important to understand wet etching reactions in the nanoscale region of solid-liquid interfaces, in order to assist in optimizing process conditions to satisfy the severe demand for semiconductor devices. Simulations performed to analyze the behavior of liquid molecules in the nanoscale region have been reported [1], but there have been few reports of detailed experimental results. We here report detailed experimental results on the wet etching behavior of SiO2 film in the nanoscale region between Si materials.

Challenges of EUVL resist process toward practical application

This paper reports the extracted risk issues on practical EUV resist processes and discusses verifications of them. The risk issues were extracted with emphasis on critical dimension, defectivity and productivity for mass production EUV resist processes. The authors verified these risk factors by utilizing available empirical knowledge. The authors found that the micro loading effect of by-product in the resist development process was a key factor for CD uniformity. Also discovered, was that high surface energy differences on the patterned wafers were a key factor for defectivity. As a result, application of scan-dynamic development and dynamic scan rinse to EUV processes on a mass production level will contribute greatly to CD and defect control as well as productivity.