Suhap Sahin

Neural network implementation in hardware using FPGAs

The usage of the FPGA (Field Programmable Gate Array) for neural network implementation provides flexibility in programmable systems. For the neural network based instrument prototype in real time application, conventional specific VLSI neural chip design suffers the limitation in time and cost. With low precision artificial neural network design, FPGAs have higher speed and smaller size for real time application than the VLSI design. In addition, artificial neural network based on FPGAs has fairly achieved with classification application. The programmability of reconfigurable FPGAs yields the availability of fast special purpose hardware for wide applications. Its programmability could set the conditions to explore new neural network algorithms and problems of a scale that would not be feasible with conventional processor. The goal of this work is to realize the hardware implementation of neural network using FPGAs. Digital system architecture is presented using Very High Speed Integrated Circuits Hardware Description Language (VHDL) and is implemented in FPGA chip. The design was tested on a FPGA demo board.

Implementation of floating point arithmetics using an FPGA

Floating point operations, which find their applications in vast areas such as many mathematical optimization methods, digital signal and image processing algorithms, and Artificial Neural Networks (ANNs), require much area and time for ordinary implementation on Field Programmable Gate Arrays (FPGAs). However, meaningful floating point arithmetic implementation on FPGAs is quite difficult with low level design specifications due to mapping difficulties and the complexity of floating point arithmetic. Design and implementation of floating point arithmetic and mapping of this into an FPGA become easier with the emergence of new generation FPGAs and development of high level languages such as VHDL tools. This paper presents the implementation methodologies of various floating point arithmetic operations such as addition, subtraction, multiplication, and division using 32-bit IEEE 754 floating point format. The implementation is performed using Xilinxs Spartan 3 FPGAs. The algorithms and implementation steps used for different operations are discussed in detail. As an example, an ANN application is presented using these algorithms.

Analyzing distributed file synchronization techniques for educational data

“Movement of Enhancing Opportunities and Improving Technology”, abbreviated as Fatih, is among the most important educational projects in Turkey, in which students and teachers can use their tablet PCs to obtain educational data (text, images, media, etc.) stored in cloud servers. However, the limited network bandwidth and increase in both the number of users and their educational data sizes degrade the system performance and even negatively affect the overall usability of the system. Proxy server is a solution approach to both decreasing network traffic and increasing the efficiency in data transfers between end users (tablets) and cloud servers. In case of using a proxy server, synchronization problems arise. In this paper, distributed file synchronization approaches such as SyncML, Rsync and CouchDB have been reviewed and compared for their feasibility of employing in this school level proxy server based distributed systems architecture.

Which number format to use for baseband Wimax Modem implementation on an FPGA

FFT/IFFT is the most important module for OFDM based baseband Wimax Modem architecture. However, computational complexity of this module is larger compared to other blocks in an OFDM system. It is critically important for the realization of this module on an FPGA that is much faster than traditional processors. In this paper, computation of CORDIC algorithm which is essential for the implementation of FFT module on FPGA, implementation using floating point and signed magnitude is studied and their performance comparison is given.

Evaluation of FPGA-based Software Radio Beamformers for 3G Wireless

This paper presents implementation of some CDMA system compatible antenna array algorithms such as least mean square (LMS), constant modulus (CM) and space code correlator (SCC) on FPGA (such as Xilinx Virtex II Pro FPGA). Implementation issues such as architecture complexity and weight vector computation times are presented. For the signal modeling, cdma2000 reverse link signal model is considered using uniform linear array (ULA) topology. Results show that FPGA based implementation provides relatively short weight vector computation times compared to previously obtained DSP based implementations

Implementation of Fast Fourier and Inverse Fast Fourier Transforms in FPGA

This article explains implementing of fast Fourier (FFT) and inverse fast Fourier transform (IFFT) algorithms in FPGA. The reason of designing the study on FPGA base is that FPGAs are able to rearrange of logical blocks and moreover, mathematical algorithms can confirm faster by means of parallel data processing. For operating these algorithms, it was used the family of Xilinx Virtex2P xc2vp30fg676-7 FPGA device as a hardware in this study. In programming the hardware and writing codes, VHDL was used. The results show that FFT and IFFT algorithms result in 0.6 mus and 0.72 mus cycle time respectively.

A Comparative Study of Antenna Array Algorithm Implementations using FPGA and DSP for cdma2000

This paper demonstrates implementation of some CDMA system compatible antenna array algorithms namely LMS and space code correlator (SCC) on an FPGA. A comparative study of FPGA and DSP implementation issues such as architecture complexity and weight vector computation time is also given. The implementations of the algorithms are performed on Xilinx Virtex II Pro FPGA and Texas Instruments (TI) TMS320C67x floating-point DSP platforms. For the signal modeling, cdma2000 reverse link signal model is considered for uniform linear array topology and varying multipath propagation conditions. Results show that the both algorithms, which were implemented on Xilinx XC2VP4 and TMS320C6713 DSP, provides weight vector computation time smaller than 10 ms period.

FPGA Implementation of Wavelet Neural Network Training with PSO/iPSO

In this study, field-programmable gate array (FPGA)-based hardware implementation of the wavelet neural network (WNN) training using particle swarm optimization (PSO) and improved particle swarm optimization (iPSO) algorithms are presented. The WNN architecture and wavelet activation function approach that is proper for the hardware implementation are suggested in the study. Using the suggested architecture and training algorithms, test operations are implemented on two different dynamic system recognition problems. From the test results obtained, it is observed that WNN architecture generalizes well and the activation function suggested has approximately the same success rate with the wavelet function defined in the literature. In the FPGA-based implementation, IEEE 754 floating-point number format is used. Experimental tests are done on Xilinx Artix 7 xc7a100t-1csg324 using ISE Webpack 14.7 program.

FPGA based implementation of CORDIC using different number format

In modern computer systems (communication systems, military systems, medical applications, etc.) are sophisticated mathematical operations and trigonometric calculations widely used. CORDIC (Coordinate Rotation DIgital Computer) architecture should be used on digital computers to implement complex mathematical operations and trigonometric calculations. In this study, two architectures called FP-CORDIC and IQCORDIC have been devised to implement CORDIC algorithm. These architectures have been realised with IEEE-754 and IQ-Math in order. Also they have been compared according to execution time, process accuracy and hardware performance criteria on FPGA.

Indoor reduction of noise in RF signal with Kalman Filter

The number of multi-storey building complex is increasing every day. Nowadays, widely used in the navigation systems position in the open space is provided by Global Positioning Satellite System GNSS. Unfortunately, the direct use of GNSS systems in indoor areas is not possible. Many technologies in the field of indoor location determination (Wireless, RF(Radio Frequency), Bluetooth, ...) have been used. This article aims to develop a minimal cost indoor positioning system. The proposed system to avoid the cost (to capture the minimum cost) to RSSI (Received Signal Strength Indicator) value using the integrated high cost of communication is used. Is not very much affected by noise RSSI information in the system used in the study. Is of vital importance to reduce signal noise projects naturally. Kalman filter system for reducing noise signal is added. The adjusted value of the noise signal in the article and the values passed to the Kalman Filter will be examined and compared.