Ali Tangel

“The CMOS Inverter” as a Comparator in ADC Designs

This paper introduces a single-ended non-offset-cancelled flash ADC architecture, the “Threshold Inverter Quantizer” (TIQ). The TIQ is based on a CMOS inverter cell, in which the voltage transfer characteristics (VTC) are changed by systematic transistor sizing. As a result, a significant improvement of speed and reduction of area and power consumption is achieved. A sample TIQ based flash ADC chip including 3-bit, 4-bit and 6-bit versions together has been designed and fabricated with the 2 μ standard CMOS n-well technology. The proposed ADC cells are suitable for System-on-Chip (SoC) applications in high speed wireless products.

A 1-GSPS CMOS flash A/D converter for system-on-chip applications

This paper presents an ultrafast CMOS flash A/D converter design and performance. Although the featured A/D converter is designed in CMOS, the performance is compatible to that of GaAs technology currently available. To achieve high-speed in CMOS, the featured A/D converter utilizes the Threshold Inverter Quantization (TIQ) technique. A 6-bit TIQ based flash A/D converter was designed with the 0.25 /spl mu/m standard CMOS technology parameter. It operates with sampling rates up to 1 GSPS, dissipates 66.87 mW of power at 2.5 V, and occupies 0.013 mm/sup 2/ area. The proposed A/D converter is suitable for System-on-Chip (SoC) applications in wireless products and other ultra high speed applications.

Future-ready ultrafast 8bit CMOS ADC for system-on-chip applications

Design and performance of an ultrafast 8bit 0.25 /spl mu/m CMOS flash ADC based on the thresholding inverter comparator are presented.

A 10-Bit 500Ms/s Two-Step Flash ADC

In this article, a novel 10-bit two-step flash A/D converter architecture based on the threshold inverter quantization technique, TIQ is presented. The simulation results include 1.5V analog input range, 30 MHz input bandwidth, and 250 mWatts of power consumption at maximum sampling rate of 500 Ms/s. The process parameter and temperature variation analysis of the converter is especially included. The DC simulation results show linearity measures of less than 0.1 LSB DNL and INL for each 5-bit flash core. The active chip area is 1.4mm2 in 0.5mum CMOS technology

All bits cross correlation attack on the Montgomery Ladder implementation of RSA

In this study, an improved, time sample cross correlation based power attack is applied on a Montgomery Ladder implementation of the RSA. In the attack, by using an implementation level property, power traces related to the all key bits are cross correlated with each other and resulting correlation values are summed and compared to a threshold to estimate the secret key of the target RSA implementation. The attack could retrieve all the key bits by using 75% lesser power traces when compared to the single fixed reference bit and 50% lesser power traces compared to the double fixed reference bits approaches which are applied on the same implementation earlier.

MOS mismatch effects on TIQ comparators

The main purpose of this study is to investigate the so-called threshold inverter quantisation (TIQ) technique from a MOS transistor mismatch point of view. The logic threshold voltage values on the voltage transfer characteristics of three different area-sized CMOS cascaded inverters located on four different locations around a TIQ-based 5b Flash ADC are measured over 40 fabricated samples in a 0.5 μm CMOS process to investigate the intra-die and inter-die mismatch effects. Based on the test results, the worst case inter-die and intra-die standard deviations occur (as 70 mV and 80 mV, respectively) when (W n/W p) has the minimum design value of (W n/W p = 3.6 μm/23.6 μm). If the mean value of percent–standard deviations are chosen as the comparison parameter, then the comparator having minimum size of transistors exhibits the worst case matching property for having 2.91% of mean percent–standard deviation value for the intra-die case. This work concludes that the suggested resolution values for TIQ-based Flash ADC designs are to be less than 6-bit for 0.5 μm CMOS process. However, it might be lesser for a smaller feature-size CMOS TIQ-based flash ADC design due to the expected increase in short channel and narrow width effects. On the other hand, if a higher resolution is preferred, then the channel length value should not be reduced to the minimum value that the related technology allows during the design process. In this situation, however, the sampling rate will be degraded.

A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology

Abstract This paper presents design and simulation of a 4-bit 10 GS/s time interleaved ADC in 0.25 micrometer CMOS technology. The designed TI-ADC has 4 channels including 4-bit flash ADC in each channel, in which area and power efficiency are targeted. Therefore, basic standard cell logic gates are preferred. Meanwhile, the aspect ratios in the gate designs are kept as small as possible considering the speed performance. In the literature, design details of the timing control circuits have not been provided, whereas the proposed timing control process is comprehensively explained and design details of the proposed timing control process are clearly presented in this study. The proposed circuits producing consecutive pulses for timing control of the input S/H switches (ie the analog demultiplexer front-end circuitry) and the very fast digital multiplexer unit at the output are the main contributions of this study. The simulation results include +0.26/−0.22 LSB of DNL and +0.01/−0.44 LSB of INL, layout area of 0.27 mm2, and power consumption of 270 mW. The provided power consumption, DNL and INL measures are observed at 100 MHz input with 10 GS/s sampling rate.

Design and implementation of a communication protocol for mobile device controlled smart home management system

Recently, with the increase in mobile and internet accessibility, it has become widespread that smart home systems can be managed remotely and monitored by mobile devices. In this study, a communication protocol between a mobil devices-embedded PC based control unit-sensors/actuators is designed and implemented. A handshaking mechanism between a mobile device and control unit, and packet structure for messaging between control unit and sensors/actuators are explained. With this system, the smart home system can be controlled over a wireless LAN by authorized users using an Android based mobile device on which the implemented GUI software is running.

A high performance PIN diode design in 0.25um SiGe HBT process

In this paper, the physical structure, application areas, and design details of PIN diodes highlighted from the literature are summarized. Moreover, the YITAL 0.25μ SiGe HBT process compatible PIN diode to be used in X-Band transmitter/receiver circuits and monolithic microwave integrated circuit applications is designed using TCAD design tools. Additionally, effects of PIN diode geometry to its performance are also addressed. The anode area of the designed PIN is 16 μm2 with square geometry. In addition to above studies, it is suggested to use of guard ring, deep trench isolation, and also a boron implantation under the bottom of each deep trench isolation well due to their positive effects on diode isolation parameters. Some important SPICE parameters are also extracted from the designed PIN diode using the completed DC and AC simulations. The related simulation results and calculations are also given in the paper together with discussions and future works.