Sujit Phatak

A Real-Time Scratchpad-Centric OS for Multi-Core Embedded Systems

Multi-core processors have replaced single-core systems in almost every segment of the industry. Unfortunately, their increased complexity often causes a loss of temporal predictability which represents a key requirement for hard real-time systems. Major sources of unpredictability are the shared low level resources, such as the memory hierarchy and the I/O subsystem. In this paper, we approach the problem of shared resource arbitration at an OS-level and propose a novel scratchpad-centric OS design for multi-core platforms. In the proposed OS, the predictable usage of shared resources across multiple cores represents a central design-time goal. Hence, we show (i) how contention-free execution of real-time tasks can be achieved on scratchpad-based architectures, and (ii) how a separation of application logic and I/O perations in the time domain can be enforced. To validate the proposed design, we implemented the proposed OS using a commercial-off-the-shelf (COTS) platform. Experiments show that this novel design delivers predictable temporal behavior to hard real-time tasks, and it improves performance up to 2.1× compared to traditional approaches.

CYBER PHYSICAL SYSTEM: A VIRTUAL CPU BASED MECHATRONIC SIMULATION

Abstract A Cyber-Physical full virtual Gasoline Fuel Pump control system was setup in a co-simulation environment by interfacing different components of the system modeled in different domains and co-simulated across a TCP/IP interface bus. The goal was to achieve a realistic implementation of the system including the microcontroller model (virtual CPU) along with other mechatronic system component models interfaced across the bus that would yield a multi-domain co-simulation platform. An evaluation and calibration of the system with and without the virtual CPU was also performed.

A Reliable and Predictable Scratchpad-centric OS for Multi-core Embedded Systems

Abstract-The reliable use of multi-core platforms for designing safety-critical systems still represents an open challenge. Recently, the FAA [1] has formally expressed its concern towards the use of multi-core systems in avionics. The sharing of hardware resources introduces non-trivial timing dependencies between logically independent components (e.g. cores); additionally, the increase in size of circuitry, memory resources, and transistor density makes these platforms more susceptible to transient memory (soft) errors. This work addresses the problem of memory soft errors and their recovery at an OS/platform level on commercial multi-core systems. Proposed strategy considers the schedulability impact of recovery procedures on hard real-time workloads. Finally, the implementation of a SPM-centric OS with the proposed OS-level strategies was performed by using a commercially available multi-core platform. The design has been validated and evaluated using a combination of synthetic and realistic (EEMBC) benchmarks.