Yasuo Sugure
Hitachi
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Featured researches published by Yasuo Sugure.
dependable systems and networks | 2011
Yohei Nakata; Yasuhiro Ito; Yasuo Sugure; Shigeru Oho; Yusuke Takeuchi; Shunsuke Okumura; Hiroshi Kawaguchi; Masahiko Yoshimoto
We propose a fault-injection system (FIS) that can inject faults such as read/write margin failures and soft errors into a SRAM environment. The fault case generator (FCG) generates time-series SRAM failures in 7T/14T or 6T SRAM, and the proposed device model and fault-injection flow are applicable for system-level verification. For evaluation, an abnormal termination rate in vehicle engine control was adopted. We confirmed that the vehicle engine control system with the 7T/14T SRAM improves system-level dependability compared with the conventional 6T SRAM.
IFAC Proceedings Volumes | 2013
Yasuo Sugure; Yasuhiro Ito; Yohei Nakata; Yusuke Takeuchi; Hiroshi Kawaguchi; Masahiko Yoshimoto; Shigeru Oho
Abstract We propose a virtual prototyping system that can evaluate failure mode and effect analysis (FMEA). The virtual prototyping system which consists of co-simulation environment between mechanics model and microcontroller model is integrated a fault-injection system that can inject faults into SRAM. This approach was applied to a validation of vehicle engine control. We observed that an abnormal system behavior occurred by SRAM fault. Thus the virtual prototyping system with fault-injection system can be performed a vehicle engine control behavior without actual components when fault occurred.
IEICE Transactions on Electronics | 2006
Yasuo Sugure; Seiji Takeuchi; Yuichi Abe; Hiromichi Yamada; Kazuya Hirayanagi; Akihiko Tomita; Kesami Hagiwara; Takeshi Kataoka; Takanori Shimura
A 32-bit embedded RISC microcontroller core targeted for automotive, industrial, and PC-peripheral applications has been developed to offer the smaller code size, lower-latency instruction and interrupt processing needed for next-generation microcontrollers. The 360MIPS/ 400MFLOPS/200 MHz core-based on the Harvard bus architecture-uses 0.13/0.15-μm CMOS technology and consists of a CPU, FPU, and register banks. To reduce the size of the control programs, new instructions have been added to the instruction set. These new instructions, as well as an enhanced C compiler, produce object files about 25% smaller than those for a previous designed core. A dual-issue superscalar structure consisting of three- or five-stage pipelines provides instruction processing with low latency. The cycle performance is thus an average of 1.8 times faster than the previous designed core. The superscalar structure is used to save 19 CPU registers in parallel when executing interrupt processing. That is, it saves the 19 CPU registers to the resister bank by accessing four registers at a time. This structure significantly improves interrupt response time from 37 cycles to 6 cycles.
Archive | 2019
Masahiko Yoshimoto; Go Matsukawa; Yohei Nakata; Hiroshi Kawaguchi; Yasuo Sugure; Shigeru Oho
This chapter presents a novel architecture for a fault-tolerant and dual modular redundancy (DMR) system using a checkpoint recovery approach. The architecture features exploitation of SRAM with simultaneous copy and instantaneous compare function. It can perform low-latency data copying between dual cores. Therefore, it can carry out fast backup and rollback. Furthermore, it can reduce the power consumption during data comparison process compared to the Cyclic Redundancy Check (CRC). Evaluation results show that compared with the conventional checkpoint/restart DMR, the proposed architecture reduces the cycle overhead by 97.8% and achieves a 3.28% low-latency execution cycle even if a one-time fault occurs when executing the task. The proposed architecture provides high reliability for systems with a real-time requirement.
Archive | 2019
Shigeru Oho; Yasuhiro Ito; Yasuo Sugure; Yohei Nakata; Hiroshi Kawaguchi; Masahiko Yoshimoto
In the coming age of self-driving cars, system-level testing of electronic control will become much more important to ensure dependable operation of automated functions. Modern VLSI devices are not always totally reliable. They can fail due to aging, electromagnetic excitation and many other reasons as described in the other chapters in this book. Therefore, dependable electronic systems must be tested against possible VLSI device failures. This may not be a common practice for meeting the ISO 26262 functional safety standard today, but deemed necessary for full-fledged self-driving cars in future. In this chapter, we demonstrate system-level simulation of SRAM errors and their impact on the design of electronic control. Automotive engine control is chosen as a test bed for this study. Model-based development techniques for automotive control systems are described first as the background and virtual electronic control units are introduced. A dependable SRAM architecture is proposed, and to test it in a practical use, a multilayer simulation modeling of an electromechanical system, its control software, and the SRAM design built-in microcontroller are discussed. To run a fault injection analysis in the SRAM chip at a large scale, a public cloud computing is used. The virtual computer machines in the cloud computing carry out the virtual engine control system simulation in which an instruction set simulator for the microcontroller executes the control software code step by step. The simulation system traces the outcome of the engine control system behavior upon a fault injection into SRAM to evaluate the dependable SRAM design. The large-scale fault analysis proposed here allows us to evaluate quantitatively the impact of the quality design of components on the entire system failure rate.
international conference on control, automation and systems | 2010
Yasuhiro Ito; Yasuo Sugure; Shigeru Oho
Virtual hardware-in-the-loop simulation (VHILS) simulation was proposed to validate real-time control software. The VHILS simulator integrated entire mechatronic control systems and dealt with multiple technology domains of mechanical, electronic, control and software. A processor simulator ran control software codes in binary format and analyzed accurately their real-time behavior. The VHILS concept was applied to an automotive adaptive cruise control system (ACCS), and driver maneuvering, vehicle dynamics, micro controller operation and CAN communication were modeled. The modeling efficiency of the serial data communication and the data exchange between the CAN model and the multi-domain simulation were identified as the primarily causes of longer computational time. By carefully designing the simulator interface and the CAN model, we successfully built a VHILS for the ACCS that agreed accurately with experimental results and yielded a practical turn-around time.
Archive | 2010
Yasuhiro Ito; Yasuo Sugure; Shigeru Oho; Hideaki Kurata
SAE International Journal of Passenger Cars - Electronic and Electrical Systems | 2009
Yasuo Sugure; Shigeru Oho; Sujit Phatak; George Saikalis
Archive | 2008
Yasuo Sugure; Donald J. McCune; Sujit Phatak; George Saikalis
SAE International Journal of Passenger Cars - Electronic and Electrical Systems | 2011
Yasuhiro Ito; Yasuo Sugure; Shigeru Oho; Masahiro Matsushita