Suk-Han Yoon

Effects of multithreading on cache performance

As the performance gap between processor and memory grows, memory latency becomes a major bottleneck in achieving high processor utilization. Multithreading has emerged as one of the most promising and exciting techniques used to tolerate memory latency by exploiting thread-level parallelism. The question, however, remains as to how effective multithreading is on tolerating memory latency. The performance of multithreading is not only affected by the overlapping of memory latency with useful computation, but also strongly depends on the cache behavior and the overhead of multithreading (e.g., thread management and context-switch costs). In particular, multithreading affects the behavior of caches, and, thus, the overall performance in a nontrivial fashion. To study these issues, this paper presents the Multithreaded Virtual Processor (MVP) model. MVP integrates the multithreaded programming paradigm and a modern superscalar processor with support for fast context switching and thread scheduling. Our studies with MVP show that, in general, the performance improvements are obtained not only by tolerating memory latency but also lower cache miss rates due to exploitation of data locality. However, multithreading creates an additional stress on the memory hierarchy caused by the interference among threads. Also, the dynamic behavior of multithreaded execution hinders the instruction locality that results in a high number of misses in the L1 instruction cache.

A preliminary performance study of architectural support for multithreading

This paper discusses the preliminary performance study of hybrid multithreaded execution model that combines software-controlled multithreaded system with hardware support for efficient context switching and threads scheduling. The hardware support for multithreading is augmented with a software thread scheduling technique called set scheduling, and their benefit to the overall performance is discussed. Set scheduling schedules multiple threads onto the hardware scheduler to minimize the software scheduling and context switching costs. An analytical model of the proposed multithreaded model is discussed and simulation results of processor utilization based on the proposed model are presented. Through simulation, we find that the hybrid multithreaded execution model results in high processor utilization than traditional software-controlled multithreading.

A Bus Arbitration Scheme With Smoothly-Distributed Waiting Time

A shared bus is a frequently-used interconnection channel, to which multiple masters can be connected. It is a single resource which can carry only one transaction at a time. So the protocol of shared buses must include a sequence of operations called arbitration which selects a unique commander. In this paper, we propose a coded self arbitration scheme that provides smoothly-distributed waiting time to all bus masters. In the proposed scheme, when there are more than one request on the shared bus, the bus master with the longest waiting time wins and the bus is allocated to the master. Each bus master requires a ⌈log2 n⌉-bit counter where n is the number of bus masters. And we have evaluated the proposed scheme and compared it with starvationfree arbitration schemes studied so far. According to our simulation, the proposed scheme shows the best distribution of waiting time reguardless of bus request rates.

An Integrated Dynamic and Visual Debugging for Parallel Applications.

We have developed a parallel debugger, ParaDebug , that integrates the traditional cyclical debugging functions and execution visualization. The user can repeatedly stop a program’s execution, examine the state, and then continue or re-execute the execution, while analyzing or animating run-time events of that program in graphical views. This is achieved by a textual/graphical view mapping technique that correlates particular source statements with the corresponding graphical view points automatically. ParaDebug is currently in use for parallel extensions of C ( ParaC ) and MPI (Message-Passing Interface) programs which run on a clustered parallel machine SPAX .

A study on logic design and architecture simulator design of a new on-chip multiprocessor

We propose a novel on-chip multiprocessor architecture and a program-driven simulator for the processor. Todays superscalar processors already have very complicated control logics to resolve dependencies while increasing the instructions per-cycle (IPC). With the advent of semiconductor technology, integrating multiple processors into a chip is a promising alternative for increasing IPC. The new architecture simulator provides a coarse grain multithreaded architecture simulation environment. It runs various multithreaded benchmark programs. We can find out how various architecture-dependent parameters affect the behavior and performance of the on-chip multiprocessor as it includes not only the instruction set architecture but also the microarchitecture.

A quantitative approach to the design of block data transfer mechanism for an SMP-based message-passing system

The authors present the performance simulation and design of block data transfer mechanism for the SMP based message passing system called SPAX (Scalable Parallel Architecture computer based on X-bar network). For node-to-node block data transfer in SPAX, two schemes of memory-mapped transfer and DMA based transfer can be considered as a design alternative of network interface architecture. According to the simulation results, the DMA based scheme is more efficient for both latency and bandwidth rather than the memory mapped scheme in transferring the block data in SPAX. We also present the design of the block data transfer mechanism based on the DMA based transfer in detail, which is applied to SPAX.