Woo-Jong Hahn

Effects of multithreading on cache performance

As the performance gap between processor and memory grows, memory latency becomes a major bottleneck in achieving high processor utilization. Multithreading has emerged as one of the most promising and exciting techniques used to tolerate memory latency by exploiting thread-level parallelism. The question, however, remains as to how effective multithreading is on tolerating memory latency. The performance of multithreading is not only affected by the overlapping of memory latency with useful computation, but also strongly depends on the cache behavior and the overhead of multithreading (e.g., thread management and context-switch costs). In particular, multithreading affects the behavior of caches, and, thus, the overall performance in a nontrivial fashion. To study these issues, this paper presents the Multithreaded Virtual Processor (MVP) model. MVP integrates the multithreaded programming paradigm and a modern superscalar processor with support for fast context switching and thread scheduling. Our studies with MVP show that, in general, the performance improvements are obtained not only by tolerating memory latency but also lower cache miss rates due to exploitation of data locality. However, multithreading creates an additional stress on the memory hierarchy caused by the interference among threads. Also, the dynamic behavior of multithreaded execution hinders the instruction locality that results in a high number of misses in the L1 instruction cache.

Performance of On-Chip Multiprocessors for Vision Tasks (Summary)

Computer vision is a challenging data intensive application. Currently, superscalar architectures dominate the processor marketplace. As more transistors become available on a single chip, the “on-chip multiprocessor” has been proposed as a promising alternative to processors based on the superscalar architecture. This paper examines the performance of vision benchmark tasks on an on-chip multiprocessor. To evaluate the performance, a program-driven simulator and its programming environment were developed. DARPA IU benchmarks were used for evaluation purposes. The benchmark includes integer, floating point, and extensive data movement operations. The simulation results show that the proposed on-chip multiprocessor can exploit thread-level parallelism effectively.

A study on logic design and architecture simulator design of a new on-chip multiprocessor

We propose a novel on-chip multiprocessor architecture and a program-driven simulator for the processor. Todays superscalar processors already have very complicated control logics to resolve dependencies while increasing the instructions per-cycle (IPC). With the advent of semiconductor technology, integrating multiple processors into a chip is a promising alternative for increasing IPC. The new architecture simulator provides a coarse grain multithreaded architecture simulation environment. It runs various multithreaded benchmark programs. We can find out how various architecture-dependent parameters affect the behavior and performance of the on-chip multiprocessor as it includes not only the instruction set architecture but also the microarchitecture.

A quantitative approach to the design of block data transfer mechanism for an SMP-based message-passing system

The authors present the performance simulation and design of block data transfer mechanism for the SMP based message passing system called SPAX (Scalable Parallel Architecture computer based on X-bar network). For node-to-node block data transfer in SPAX, two schemes of memory-mapped transfer and DMA based transfer can be considered as a design alternative of network interface architecture. According to the simulation results, the DMA based scheme is more efficient for both latency and bandwidth rather than the memory mapped scheme in transferring the block data in SPAX. We also present the design of the block data transfer mechanism based on the DMA based transfer in detail, which is applied to SPAX.

Modeling and evaluation of a new cluster-based system for commercial applications

We model and evaluate a new parallel processing system for commercial applications, so called SPAX. SPAX cost-effectively overcomes the SMP limitation by providing both scalability of the parallel processing system and application portability of the SMP. To investigate whether the new architecture satisfies the requirements of commercial applications, such as OLTP, we have built the system and workload model. The results of the simulation show that the IO subsystem becomes the bottleneck before the newly developed system network. We find that SPAX can still meet the IO requirement of the OLTP workload as its network and IO node support the flexible IO subsystem, in terms of the number of disk drives and IO nodes versus that of processing nodes.