Sule Ozev

Ensuring the operational health of droplet-based microelectrofluidic biosensor systems

Recent events have heightened the need for fast, accurate, and reliable biological/chemical sensor systems for critical locations. As droplet-based microelectrofluidic sensor systems become widespread in these safety-critical biomedical applications, reliability emerges as a critical performance parameter. In order to ensure the operational health of such safety-critical systems, they need to be monitored for defects, not only after manufacturing, but also during in-field operation. In this paper, we present a cost-effective concurrent test methodology for droplet-based microelectrofluidic systems. We present a classification of catastrophic and parametric faults in such systems and show how faults can be detected by electrostatically controlling and tracking droplet motion. We then present a fault simulation approach based on tolerance analysis using Monte-Carlo simulation to characterize the impact of parameter variations on system performance. Finally, we present experimental results on a droplet-based microelectrofluidic system for a real-time polymerase chain reaction application.

Concurrent testing of droplet-based microfluidic systems for multiplexed biomedical assays

We present a concurrent testing methodology for detecting catastrophic faults in droplet-based microfluidic systems and investigate the related problems of test planning and resource optimization. We apply this methodology to a droplet-based microfluidic array that was fabricated and used to perform multiplexed glucose and lactate assays. The test approach interleaves test application with the biomedical assays and prevents resource conflicts. We show that an integer linear programming model can be used to minimize testing time for a given hardware overhead due to droplet dispensing sources and capacitive sensing circuitry. The proposed approach is therefore directed at ensuring high reliability and availability of bio-MEMS and lab-on-a-chip systems, as they are increasingly deployed for safety-critical applications.

Concurrent testing of digital microfluidics-based biochips

We present a concurrent testing methodology for detecting catastrophic faults in digital microfluidics-based biochips and investigate the related problems of test planning and resource optimization. We first show that an integer linear programming model can be used to minimize testing time for a given hardware overhead, for example, droplet dispensing sources and capacitive sensing circuitry. Due to the NP-complete nature of the problem, we also develop efficient heuristic procedures to solve this optimization problem. We apply the proposed concurrent testing methodology to a droplet-based microfluidic array that was fabricated and used to perform multiplexed glucose and lactate assays. Experimental results show that the proposed test approach interleaves test application with the biomedical assays and prevents resource conflicts. The proposed method is therefore directed at ensuring high reliability and availability of bio-MEMS and lab-on-a-chip systems, as they are increasingly deployed for safety-critical applications.

Test planning and test resource optimization for droplet-based microfluidic systems

Recent years have seen the emergence of droplet-based microfluidic systems for safety-critical biomedical applications. In order to ensure reliability, microsystems incorporating microfluidic components must be tested adequately. In this paper, we investigate test planning and test resource optimization methods for droplet-based microfluidic arrays. We first outline a methodology based on integer linear programming (ILP) that yields optimal solutions. Due to the NP-complete nature of the problem, we develop heuristic approaches for optimization. Experimental results indicate that for large array sizes, heuristic methods yield solutions that are close to provable lower bounds. These heuristics ensure scalability and low computation cost.

Wafer-level RF test and DfT for VCO modulating transceiver architectures

Traditionally, radio frequency (RF) paths are bypassed during wafer sort due to the high cost of RF testing. Increasing packaging costs, however; result in a need for a more thorough wafer-level testing including the RF path. In this paper, we propose a loop-back architecture, along with a novel, all-digital design-for-testability (DfT) modification that enables cost efficient testing of various defects at the wafer level. These methods are applicable to a wide range of cost-sensitive applications that use the modulation of the voltage-controlled-oscillator (VCO). Experimental results using a Bluetooth platform and considering a variety of defects confirm the viability of the approach.

Statistical Test Development for Analog Circuits Under High Process Variations

The test development efforts for analog circuits today are disproportionately high due to the lack of widely accepted automation methods. The evaluation of a particular test input and measurement setup requires the determination of the probabilistic detection of all faults in the circuit. This evaluation step is the most time consuming step during analog test development. Based on the observation that test evaluation requires injecting many parametric and catastrophic faults into the circuit and analyzing the masking effect of process variations, we develop a fault injection and simulation technique for analog circuits that is specifically geared toward information reuse. We also present a heuristic test selection methodology that aims at providing the same coverage level as the full specification measurements while reducing the test time as well as reliance on hard-to-measure parameters. Experimental results on several circuits confirm the high accuracy of our variance analysis technique and show a nearly 72% reduction in the number of tests for a three-stage amplifier circuit in the experiment after the application of the test selection algorithm.

Test Planning and Test Resource Optimization for Droplet-Based Microfluidic Systems

Recent years have seen the emergence of droplet-based microfluidic systems for safety-critical biomedical applications. In order to ensure reliability, microsystems incorporating microfluidic components must be tested adequately. In this paper, we investigate test planning and test resource optimization for droplet-based microfluidic arrays. We first formulate the test planning problem and prove that it is NP-hard. We then describe an optimization method based on integer linear programming (ILP) that yields optimal solutions. Due to the NP-hard nature of the problem, we develop heuristic approaches for optimization. Experimental results indicate that for large array sizes, the heuristic methods yield solutions that are close to provable lower bounds. These heuristics ensure scalability and low computation cost.

An ADC-BiST scheme using sequential code analysis

This paper presents a built-in self-test (BiST) scheme for analog to digital converters (ADC) based on a linear ramp generator and efficient output analysis. The proposed analysis method is an alternative to histogram based analysis techniques to provide test time improvements, especially when the resources are scarce. In addition to the measurement of DNL and INL, non-monotonic behavior can also be detected with the proposed technique. We present two implementation options based on how much on-chip resources are available. The ramp generator has a high linearity over a full-scale range of IV and the generated ramp signal is capable of testing 13-bit ADCs. The circuit implementation of the ramp generator utilizes a feedback configuration to improve the linearity having an area of 0.017mm2 in 0.5mum process

Parametric fault diagnosis for analog circuits using a Bayesian framework

In this paper, we present a parametric fault diagnosis approach for analog/RF circuits based on a Bayesian framework. The Bayesian fault diagnosis requires extensive statistical profiling which is enabled by a an efficient hierarchical process variability analysis. Both DC and AC parameters are used as measurements to provide maximum diagnostic resolution. A sensitivity guided test input selection scheme is used to determine the measurement attributes that are most likely to distinguish among the faults. Fault dictionaries are constructed using parametric faults at the transistor level that have both marginal and higher deviations. During the diagnosis step, additional online profiling helps increase the diagnostic resolution. Experiments on a transistor level amplifier circuit confirms that the approach is accurate in terms of statistical attributes and most deviations in layout and process level parameters can be correctly diagnosed.

Enhanced error vector magnitude (EVM) measurements for testing WLAN transceivers

As wireless LAN devices become more prevalent in the consumer electronics market, there is an ever increasing pressure to reduce their overall cost. The test cost of such devices is an appreciable percentage of the overall cost, which typically results from the high number of specifications, the high number of distinct test set-ups and equipment pieces that need to be used, and the high cost of each test set-up. In this paper, we investigate the versatility of EVM measurements to test the variable-envelope WLAN (wireless local area networks) receiver and transmitter characteristics. The goal is to optimize EVM test parameters (input data and test limits) and to reduce the number of specification measurements that require high test times and/or expensive test equipment. Our analysis shows that enhanced EVM measurements (optimized data sequence and limits, use of RMS, scale, and phase error vector values) in conjunction with a set of simple path measurements (input-output impedances) can provide the desired fault coverage while eliminating lengthy spectrum mask and noise figure tests