Alex Orailoglu

Transformation-based high-level synthesis of fault-tolerant ASICs

The authors present a transformation-based approach to the high-level synthesis of fault-tolerant application-specific ICs (ASICs) satisfying a given performance constraint but requiring less than proportional increase in hardware over their nonredundant counterparts. They propose a synthesis methodology to exploit hardware minimizing transformations. A simple set of transformations are identified that minimize the fault-tolerance overhead. The selected transformations make the final design resilient to common mode failures. These transformations can be composed to form a rich set of complex transformations. An algorithm is presented to automatically identify structures in a flow graph where transformations can improve hardware utilization, and transformations that suit the structure best are applied. The system has been used to schedule several flow graphs.<<ETX>>

Compacting test responses for deeply embedded SoC cores

Test bandwidth allocation issues greatly limit the parallel testing of SoC cores. Here, the authors propose a response compaction methodology for reducing the required output core bandwidth, enabling increased parallelism among core tests and hence reducing the overall SoC test time.

Computer-aided design of fault-tolerant VLSI systems

The authors present a flexible methodology for compiling an algorithmic description into an equivalent fault-tolerant VLSI circuit and a CAD framework embodying this methodology. Experimental designs illustrate and validate algorithms for automated synthesis of ICs featuring either self-recovery capability or enhanced reliability.

Forward discrete probability propagation method for device performance characterization under process variations

Process variations are becoming influential at the device level in deep sub-micron and sub-wavelength design regimes, whereas they used to be a few generations away only influential at circuit level. Process variations cause device performance parameters, such as current or output resistance, to acquire a probability distribution. Estimation of these distributions has been accomplished using Monte Carlo techniques so far. The large number of samples needed by Monte Carlo methods adversely affects the possibility of integrating probabilistic device performance at the circuit level due to run-time inefficiency. In this paper, we introduce a novel technique called forward discrete probability propagation (FDPP). This method discretizes the probability distributions and effectively propagates these probabilities across a device formula hierarchy, such as the one present in the SPICE3v3 model. Consequently, probability distributions for process parameters are propagated to the device level. It is shown in the paper that with far fewer number of samples, comparable accuracy to a Monte Carlo method is achieved.

Application-specific instruction memory customizations for power-efficient embedded processors

An encoding technique exploits application information to reduce power consumption along the instruction memory communication path in embedded processors. Microarchitectural support enables reprogrammability of the encoding transformations to track specific code effectively, and the restriction to functional transformations delivers major power savings. Having reprogrammable hardware also allows flexible, inexpensive switches between transformations.

A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs

A design for test (DFT) hardware is proposed to increase the controllability of a thermometer coded current steering digital to analog converter. A procedure is introduced to reduce the diagnosis and structural test time from quadratic to linear using the proposed DFT hardware. To evaluate the applicability of the proposed technique, principal component analysis is used to create virtual process variations to simulate in lieu of semiconductor fabrication data. An architecture specific soft fault model is suggested for the diagnosis problem. Random errors according to the fault model are introduced in the virtual test environment on top of the process variations and it is shown that diagnosis of a fault is possible with high accuracy with the proposed method. The same technique employing principal component analysis is furthermore used to provide process variation-aware reference test comparison values for a structural test of the DAC. The structural test provides a mechanism to test for even unmodeled manufacturing faults. The process variation-aware test values help detect defects even under process variations. The proposed DFT hardware and method are low cost and quite suitable for a built-in self diagnosis and test implementation.

Partial Core Encryption for Performance-Efficient Test of SOCs

The isolation of a core through full I/O scan helps ease SOC test challenges;yet the performance of high-speed SOCs is significantly hampered.We propose a partial core encryption methodology wherein thecore vendor unveils only a small part of the core logic, successfully satisfyingcore IP protection requirements. Once the partially encryptedcores are merged into an SOC, the system integrator performs test generationon the visible SOC logic only, greatly reducing the test generationeffort expended. By utilizing the test data provided by the core vendoras well, the SOC integrator can test the SOC with no performancedegradation. We present an efficient fault analysis based core encryptionalgorithm which is guided by judiciously computed testability measures.The experimental results confirm the significantly high encryption levelsattained by the proposed encryption algorithm.

Transformation-based register optimization in high-level synthesis

A novel approach to temporary register minimization that exploits the power of behavioral transformations is proposed. Behavioral transformations allow one to reduce the register requirements below the inherent lower bound imposed by the structure of the input flow graph. Specifically, the transformations minimize the lifetimes of registers in a scheduled flow graph. The transformations are applied across clock cycle boundaries with peak register use. Preliminary results for the benchmark examples show a significant reduction in the number of registers.<<ETX>>

Simulated annealing based yield enhancement of layouts

This paper presents DEFT, a system for synthesizing defect-tolerant layouts, that in-grains tolerance to fabrication induced defects. This is accomplished by dispersing nets with large overlaps into nonadjacent tracks. DEFT also affords trade-offs between area (measured as the number of tracks) and yield of the resulting layout. The defect-tolerant layouts synthesized by DEFT have been consistently superior to those generated by other layout synthesis systems.<<ETX>>

Autonomous yet deterministic test of SOC cores

Increased core test parallelism translates into reduced SOC test application time; yet the availability of a limited number of tester channels hampers this parallelism. Furthermore, the test vectors to be delivered into core scan chains need to be stored in the tester memory, imposing considerable costs on SOC tests. We propose an SOC test methodology delivering all the benefits of core self-test, while ensuring fault coverage levels identical to those attained in deterministic test. In the proposed methodology, a single LFSR broadcasts pseudo-random patterns to each core; the LFSR patterns are transformed into the actual test vectors of a core while they are being shifted into the core scan chain. The transformation is realized through the logic gates inserted between the core scan cells. The efficacy and the cost-effectiveness of the proposed methodology reflects into significantly reduced test costs.