Sumanta Pyne

Fuzzy logic based route optimization in a multihomed mobile networks

The present work is a fuzzy logic based route optimization in multihomed mobile network. The mobile routers in the mobile network use best egress determination algorithm to identify its best egress interface for each service type supported by the mobile network dynamically and send the best egress interface per service type information to a local fixed node inside the mobile network. The mobile network node sends a request message to the local fixed node inside the mobile network to initiate a session. The local fixed node uses best route selection algorithm to select an optimal route from mobile network to Internet for the desired service type of the mobile network node. The performance of the proposed work is evaluated using NEMO_SIM simulator which is implemented using JAVA. Results based on a detailed performance evaluation study are also presented to demonstrate the efficacy of the proposed scheme.

Distributed Route Selection Algorithm in Nested Multihomed Mobile Networks

The present work is a distributed route selection algorithm in nested multihomed mobile networks. The mobile network node sends a request message to all leaf mobile routers inside the mobile network to initiate a session. All leaf mobile routers execute route selection algorithm to select the best route for the desired session of the mobile network node and send the best route to the mobile network node. The mobile network node transmits the packets corresponding to the desired session using the best route to Internet. The mobile routers associated with the best route execute egress interface selection algorithm to select the best egress interface and deliver the packets corresponding to the desired session of the mobile network node using the best egress interface to the next hop of the selected route. The performance of the proposed work is evaluated on the basis of throughput, session loss and route selection time using NEMO\_SIM simulator. Results based on a detailed performance evaluation study are also presented to demonstrate the efficacy of the proposed scheme.

Runtime Leakage Power Reduction Using Loop Unrolling and Fine Grained Power Gating

The present work introduces a compilation technique to reduce runtime leakage power of functional units of a processor by combining loop unrolling with power gating. The instructions in the unrolled loop are scheduled to provide opportunities for power gating the functional units which are not used for a considerable amount of time. An algorithm that saves maximum leakage energy without performance loss due to execution of power gating instructions has been introduced. The algorithm does loop unrolling, scheduling of instructions and finally insert power gating instructions. The present work is explained using two illustrative examples, one without loop-carried dependence and the other with loop-carried dependence. It is observed that the number of clock cycles taken by the power gating instructions is less than or equal to the number of clock cycles saved by loop unrolling. This results in 23–64% reduction of the total energy consumed by the benchmark programs without any degradation of performance.

Loop unrolling with fine grained power gating for runtime leakage power reduction

The present work introduces a compilation technique to reduce runtime leakage power of functional units of a processor by combining loop unrolling with power gating. The instructions in the unrolled loop are scheduled to provide opportunities for power gating the functional units which are not in need for a considerable amount of time. The number of clock cycles taken by the power gating instructions is less than or equal to the number of clock cycles saved by loop unrolling. This results in 23-64% reduction of the total energy consumed by the benchmark programs without any degradation of performance.

Energy Efficient Array Initialization Using Loop Unrolling with Partial Gray Code Sequence

The present work introduces a software technique to reduce energy consumed by the address bus of the on-chip data memory. This is done by reducing switching activity on the address bus of the on-chip data memory, with the help of loop unrolling with partial Gray code sequence. The present work introduces the translation of a loop with array initialization to its loop unrolled version with partial Gray code sequence. The expressions for switching activity consumed on the address bus of data memory are derived for both unrolled loop with and without partial Gray code sequence. The proposed translation method finds a relocatable base address of the array so that the partial Gray code sequence is maintained, without any energy-performance overhead and achieves a considerable amount of energy reduction without any performance loss. The proposed method achieves 25-50% reduction in switching activity on the address bus of on-chip data memory. The present work is evaluated on five benchmark programs and is suitable for programs where array initialization time is more than computation time.

Branch Target Buffer Energy Reduction Through Efficient Multiway Branch Translation Techniques

Branch Target Buffer (BTB) plays an important role for pipelined processors in branch prediction during the execution of loops, if-then-else, call-return, and multiway branch statements. It has been observed that 20% of instructions in a program are related to branch. Access to BTB consumes 10% of total energy consumption of a program in execution. The present work introduces the use of K–d tree and pattern matcher to generate efficient code, i.e., lesser execution time, for multiway branch. However, instead of enhancing performance, Voltage Frequency Scaling (VFS) can be applied to achieve energy efficiency without degradation in performance. The present work is evaluated on a wide range benchmark programs. The BTB energy saving in the present work lies in the range 20% to 80% with small improvement performance as well. The total energy reduction is in the range 3–12%.

Realization of power aware software prefetching as a multi-objective optimization problem

Software prefetching is a performance-oriented optimization technique, which is generally used to reduce the gap between processor speed and memory access speed. When software prefetching is applied to memory-intensive benchmark programs, the performance improves with higher power consumption. The present work provides a mechanism to transform a program with software prefetching to its power-aware equivalent. This is done by executing the software prefetching program at different voltage-frequency pairs. Besides reducing the power, the performance has been improved by adjusting the prefetch distance. XEEMU-Panalyzer simulator is used to evaluate the present work. Experimental results of the proposed scheme guarantees that performance improvement of software prefetching program is possible at the cost of less power consumption. The proposed work can enable a compiler to generate power aware software prefetching program.