Ajit Pal

Optimal assignment of high threshold voltage for synthesizing dual threshold CMOS circuits

Development of the process technology for dual threshold (dual V/sub th/) CMOS circuit has opened up the possibility of using it to reduce static power in low voltage high performance circuits. It has been demonstrated that by using transistors of a low threshold voltage for gates on the critical path, and by using a high threshold voltage for gates in the off-critical path it is possible to significantly reduce leakage power consumption of a circuit without performance degradation. In this paper we have a new algorithm to realize dual CMOS circuits. Our algorithm produces significantly better results for ISCAS benchmark circuits compared to reported results.

Resolving horizontal constraints and minimizing net wire length for multi-layer channel routing

The channel routing problem in VLSI design is to route a specified interconnection among modules in as small an area as possible. Hashimoto and Stevens (1971) proposed an algorithm for solving the two-layer channel routing problem in the absence of vertical constraints. In this paper, we analyze this algorithm in two different ways. In the first analysis, we show that a graph-theoretic realization, algorithm MCC1, runs in O(m + n + e) time, where m is the size of the channel specification of n nets, and e is the size of the complement of the horizontal constraint graph. In the second analysis, algorithm MCC2, we show that a time complexity of O(m + n log n) can be achieved. Algorithms MCC1 and MCC2 guarantee optimum routing solutions under the multi-layer V/sub i+1/H/sub i/ (i/spl ges/1) routing model, where the horizontal and vertical layers of interconnect alternate. Finally, we consider the problem of minimizing the total net wire length in the V/sub i+1/H/sub i/ (i/spl ges/1) routing model. Given a channel specification and a partition of the set of nets (where the nets within each part of the partition are non-overlapping), we propose an O(m + d/sub max/log d/sub max/) time algorithm for minimizing the total net wire length, subject to the condition that nets from a part of the partition are assigned to the same track. All our solutions use the minimum number of via holes.<<ETX>>

Traffic grooming, routing, and wavelength assignment in an optical WDM mesh networks based on clique partitioning

In wavelength routed optical networks, the number of wavelength channels is limited due to several constraints and each wavelength as well as each lightpath support traffic in the Gbps range. On the other hand, the traffic requested by an individual connection is still in the Mbps range. Therefore, to utilize the network resources (such as bandwidth and transceivers) effectively, several low-speed traffic streams have to be efficiently groomed or multiplexed into one or more high-speed lightpaths. The grooming problem of a static demand is considered as an optimization problem. In this work, we have investigated the traffic grooming problem with the objective of maximizing the network throughput for wavelength-routed mesh networks and map this problem to the clique partitioning problem. We have proposed an algorithm to handle general multi-hop static traffic grooming based on the clique partitioning concept. The efficiency of our approach has been established through extensive simulation on different sets of traffic demands with different bandwidth granularities for different network topologies and compared the approach with existing algorithms.

A general graph theoretic framework for multi-layer channel routing

In this paper we propose a general framework for viewing a class of heuristics for track assignment in channel routing from a purely graph theoretic angle. Within this framework we propose algorithms for computing routing solutions using optimal or near optimal number of tracks for several well-known benchmark channels in the two-layer VH. Three-layer HVH, and multi-layer V/sub i/H/sub i/ and V/sub i/H/sub i+1/ routing models. Within the same framework we also design an algorithm for minimizing the total wire length in the two-layer VH and three-layer HVH routing models.

Distributed dynamic grooming routing and wavelength assignment in WDM optical mesh networks

The bandwidth of a wavelength channel in WDM optical networks is very high compared to the user’s requirements for various applications. Therefore, there is a scope for better utilization of channel bandwidth by traffic grooming, in which several user’s channels are multiplexed for transmission over a single channel. Several research works have been reported on traffic grooming routing and wavelength assignment (GRWA) for static and dynamic traffic pattern under centralized environment. Distributed dynamic grooming routing and wavelength assignment (DDGRWA) is a new and quite unexplored area in WDM optical mesh networks. This article introduces the concept of distributed traffic grooming in WDM mesh networks which also includes virtual topology construction, reconfiguration, routing and wavelength assignment in the distributed environment assuming incoming traffic to be dynamic in nature. We have also presented simulation results of our algorithm on dynamically generated traffic under various network topologies.

Optimal dual-V/sub T/ assignment for low-voltage energy-constrained CMOS circuits

In this paper we have addressed the problem of realizing dual-V/sub T/ CMOS circuits for battery-operated hand held and portable systems. As the battery life is of primary concern, an algorithm is proposed to realize circuits with near minimal energy requirement in the standby mode as well as in the active mode, at the expense of some performance. An efficient algorithm for dual-V/sub T/ assignment has been developed, which assigns high-V/sub T/ to larger number of transistors compared to the existing approaches, leading to higher reduction in power. Experiments have been carried out to study the reduction in power requirement with the increase in delay (with corresponding increase in low-V/sub T/) compared to the highest performance single-V/sub T/ realization. Our algorithm has been tested using standard ISCAS benchmark circuits. Experimental results have established that, by compromising small performance (5 to 10% increase in delay), it is possible to realize CMOS circuits using dual-V/sub T/ technology with near-minimal energy requirement.

Formal Verification of Architectural Power Intent

This paper presents a verification framework that attempts to bridge the disconnect between high-level properties capturing the architectural power management strategy and the implementation of the power management control logic using low-level per-domain control signals. The novelty of the proposed framework is in demonstrating that the architectural power intent properties developed using high-level artifacts can be automatically translated into properties over low-level control sequences gleaned from UPF specifications of power domains, and that the resulting properties can be used to formally verify the global on-chip power management logic. The proposed translation uses a considerable amount of domain knowledge and is also not purely syntactic, because it requires formal extraction of timing information for the low-level control sequences. We present a tool, called POWER-TRUCTOR which enables the proposed framework, and several test cases of significant complexity to demonstrate the feasibility of the proposed framework.

Leveraging UPF-extracted assertions for modeling and formal verification of architectural power intent

Recent research has indicated ways of using UPF specifications for extracting valid low-level control sequences to express the transitions between the power states of individual domains. Today there is a disconnect between the high-level architectural power management strategy which relates multiple power domains and these low-level assertions for controlling individual power domains. In this paper we attempt to bridge this disconnect by leveraging the low-level per-domain assertions for translating architectural power intent properties into global assertions over low-level signals. We show that the inter-domain properties created in this manner can be formally verified over the global power management logic.

Dynamic location management with variable size location areas

This paper introduces a dynamic location management algorithm with variable size location areas (LAs), which helps in reducing location update (LU) cost and hence total location management cost. Basically there are two types of location management strategies - Static and Dynamic. In the static strategy (used in GSM), LAs consist of static and arbitrarily defined collections of cells, which do not take into account individual subscribers mobility pattern and hence these LAs remain same for all the subscribers. Since mobility pattern of an individual subscriber may differ significantly, this approach is far from optimal. Proposed location management algorithm uses the mobility history of individual subscribers to dynamically form individualized LAs based on his previous movements from cell to cell. It defines the size of LAs based on subscribers speed and call arrival probability. An activity-based mobility model is developed to test the proposed algorithm and the performance of this algorithm is compared with other algorithms, like fixed location strategy, grid-based location management strategy and dynamic location management algorithm. Overall, the proposed algorithm incurred significantly lower location management cost, in terms of signaling messages generated, as compared to all other algorithms.

NP-Completeness of Multi-Layer No-Dogleg Channel Routing and an Efficient Heuristic

In this paper we show that given a channel specification of density d,,,, the problem of determinin whether there is a routing solution using [dmar/2f tracks an the four-layer no-dogleg VHVH Manhattan routing model is NP-complete. A similar result is derived also for the six-layer VHVHVH routing model, where we wish to determine whether there is a routing solution using [d,,,/3] tracks. We also propose an efficient polynomial time heuristic for computing a multi-layer routing solution for a given channel specification. Our heuristic computes optimal multi-layer solutions for several benchmark problems.