Sundaravarathan R. Iyengar

Controller for two-way set associative cache

Method and apparatus for selecting a mode for updating external memory

Apparatus and method for updating LRU pointer in a controller for two-way set associative cache

Tag initialization in a controller for two-way set associative cache

Increasing Power Efficiency Of Turbo Mode Operation In A Processor

System and method having processor with selectable burst or no-burst write back mode depending upon signal indicating the system is configured to accept bit width larger than the bus width

EFFICIENT FREQUENCY BOOST OPERATION

LRU pointer updating in a controller for two-way set associative cache

Processor cycle tracking in a controller for two-way set associative cache

Identification of the distinction between the beginning of a new write back cycle and an ongoing write cycle