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international conference on computer design | 1989

Computer aided design and built in self test on the i486 CPU

Patrick Gelsinger; Sudarshan Iyengar; Joseph C. Krauskopf; James Nadir

The computer-aided design tools created to accelerate the design of the i486 CPU are described. Emphasis is on the logic synthesis, layout synthesis, and timing verification programs. The impact of the state-of-the-art tools on the project schedule is described, and the built-in self-test features on the processor are detailed. The type of advanced tools that will be required to design and test future processors, which will be more complex, is considered.<<ETX>>


Archive | 1981

System bus arbitration, circuitry and methodology

James Nadir


Archive | 1995

Opportunistic time-borrowing domino logic

David Money Harris; Sunny Huang; James Nadir; Ching-Hua Chu; Jason Stinson; Alper Ilkbahar


Archive | 1990

Controller for two-way set associative cache

John H. Crawford; Sundaravarathan R. Iyengar; James Nadir


Archive | 1991

Cache controller that alternately selects for presentation to a tag RAM a current address latch and a next address latch which hold addresses captured on an input bus

Yong Lee; Nagraj Palasamudram; James Nadir


Archive | 1993

Method and apparatus for overlapped timing of cache operations including reading and writing with parity checking

James Nadir; Ching-Hua Chu


Archive | 1993

Circuit and method for selecting a set in a set associative cache

James Nadir; Ching-Hua Chu


Archive | 1996

Multiport high speed memory having contention arbitration capability without standby delay

James Nadir; Ching-Hua Chu


Archive | 1995

Apparatus and method for updating LRU pointer in a controller for two-way set associative cache

Sundaravarathan R. Iyengar; James Nadir


Archive | 1994

Tag initialization in a controller for two-way set associative cache

Sundaravarathan R. Iyengar; James Nadir

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