Sung-Mo Kang

Memristive devices and systems

A broad generalization of memristors--a recently postulated circuit element--to an interesting class of nonlinear dynamical systems called memristive systems is introduced. These systems are unconventional in the sense that while they behave like resistive devices, they can be endowed with a rather exotic variety of dynamic characteristics. While possessing memory and exhibiting small-signal inductive or capacitive effects, they are incapable of energy discharge and they introduce no phase shift between the input and output waveforms. This zero-crossing property gives rise to a Lissajous figure which always passes through the origin. Memristive systems are hysteretic in the sense that their Lissajous figures vary with the excitation frequency. At very low frequencies, memristive systems are indistinguishable from nonlinear resistors while at extremely high frequencies, they reduce to linear resistors. These anomalous properties have misled and prevented the identification of many memristive devices and systems-including the thermistor, the Hodgkin-Huxley membrane circuit model, and the discharge tubes. Generic properties of memristive systems are derived and a canonic dynamical system model is presented along with an explicit algorithm for identifying the model parameters and functions.

An exact solution to the transistor sizing problem for CMOS circuits using convex optimization

A general sequential circuit consists of a number of combinational stages that lie between latches. For the circuit to meet a given clocking specification, it is necessary for each combinational stage to satisfy a certain delay requirement. Roughly speaking, increasing the sizes of some transistors in a stage reduces the delay, with the penalty of increased area. The problem of transistor sizing is to minimize the area of a combinational stage, subject to its delay being less than a given specification. Although this problem has been recognized as a convex programming problem, most existing approaches do not take full advantage of this fact, and often give nonoptimal results. An efficient convex optimization algorithm has been used here. This algorithm is guaranteed to find the exact solution to the convex programming problem. We have also improved upon existing methods for computing the circuit delay as an Elmore time constant, to achieve higher accuracy, CMOS circuit examples, including a combinational circuit with 832 transistors are presented to demonstrate the efficacy of the new algorithm. >

Accurate simulation of power dissipation in VLSI circuits

It becomes increasingly more important to reduce the power dissipation as the number of devices in VLSI increases. Accurate simulation of power dissipation is desirable while circuits are analyzed with circuit simulators such as SPICE. An accurate method is presented for simulating the power dissipation with use of a dependent current source and a parallel RC circuit. The steady-state voltage across the capacitor reads the average power drawn from the supply voltage source. Simulation results are shown for CMOS circuits.

Memristor Applications for Programmable Analog ICs

This paper demonstrates that memristors can be used to implement programmable analog circuits, leveraging memristors fine-resolution programmable resistance without causing perturbations due to parasitic components. Fine-resolution programmable resistance is achieved by varying the amount of flux across memristors. The resistance programming can be achieved by controlling the input pulsewidth and its frequency. For demonstration, a memristor is designed for a pulse-programmable midband differential gain amplifier with fine resolution.

Cell-level placement for improving substrate thermal distribution

The dramatic increase of power consumption in very large scale integration circuits has led to high operating temperature and large thermal gradient, thereby resulting in serious timing and reliability concerns. Temperature-tracking is thus becoming of paramount importance in modern electronic design automation (EDA) tools. In this paper we present two thermal placement tools for standard cell and macro cell design styles respectively. They are aimed at reducing hot spots in a design without compromising traditional design metrics such as area and wire length. We developed a compact substrate thermal model that can be used by the placer to calculate the temperature profile of a placement efficiently, or to convert the user-specified temperature constraint into the corresponding power distribution constraint as an alternative placement objective. As a result, our method is much more efficient than directly employing temperature profile simulation during the placement process. The simulation results show noticeable improvement of thermal distribution over the traditional placement algorithm, with little impact on area and wire length of the final layout.

Metal--Metal Matrix (M /sup 3/) for High-Speed MOS VLSI Layout

This paper proposes a new layout method for high-speed VLSI circuits in single-poly and double-metal MOS technology. With emphasis on the speed performance, our Metal-Metal Matrix (M /sup 3/) layout method employs maximal use of metal interconnections while restricting delay-consuming polysilicon or polycide features only to form MOS transistor gates or to connect the same type of transistor gates with common input signals. M /sup 3/ layout is also amenable to submicron technology trends and existing CAD tools for single-poly and single-metal chip assembly and routing. Our layout studies indicate that M /sup 3/ is particularly appealing to high-speed dynamic CMOS circuits in view of packing density and speed performance. This new structure has not been experimented with VLSI chip fabrication yet and awaits empirical verification.

Coupling-driven signal encoding scheme for low-power interface design

Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and system-on-a-chip (SoC) designs. A new low-power bus encoding scheme is proposed to minimize coupled switchings which dominate the on-chip bus power consumption. The coupling-driven bus invert method use slim encoder and decoder architecture to minimize the hardware overhead. Experimental results indicate that our encoding methods save effective switchings as much as 30% in an 8-bit bus with one-cycle redundancy.

Compact Models for Memristors Based on Charge-Flux Constitutive Relationships

This paper introduces compact models for memristors. The models are developed based on the fundamental constitutive relationships between charge and flux of memristors. The modeling process, with a few simple steps, is introduced. For memristors with limited resistance ranges, a simple method to find their constitutive relationships is discussed, and examples of compact models are shown for both current-controlled and voltage-controlled memristors. Our models satisfy all of the memristor properties such as frequency dependent hysteresis behaviors and also unique boundary assurance to simulate memristors whether they behave memristively or resistively. Our models are implementable in circuit simulators, including SPICE, Verilog-A, and Spectre.

Modeling and simulation of interconnection delays and crosstalks in high-speed integrated circuits

A computer model for n parallel microstrip lines is developed for circuit simulation. This model for the lossy transmission line system can be readily implemented into circuit simulators and can accurately simulate the delay and crosstalk effects of interconnects in high-speed integrated circuits. Modal analysis is applied to decouple the n-coupled-line system into n independent lines, and the characteristic solutions of telegraph equations are represented by a set of simple time-varying equivalent circuits. The model has been implemented in a general-purpose circuit simulator, iSMILE, which is compatible with SPICE. Simulation results on propagation delay times and crosstalk are presented for high-speed GaAs HEMT (high-electron-mobility transistor) integrated circuits. >

ILLIADS-T: an electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips

In this paper, we present a new chip-level electrothermal timing simulator for CMOS VLSI circuits. Given the chip layout, the packaging specification, and the periodic input signal pattern, it finds the on-chip steady-state temperature profile and the resulting circuit performance. A tester chip has been designed for verification of ILLIADS-T, and very good agreement between simulation and experiment was found. Using this electrothermal simulator, temperature-dependent reliability and timing problems of VLSI circuits can be accurately identified.