Sung-wook Park

Considering physical mechanisms and geometry dependencies in 14nm FinFET circuit aging and product validations

We report the extensive 14nm FinFET reliability characterization work and provide physical mechanisms and geometry dependencies. BTI, HCI variability related to #of Fin used in design along with self-heat considerations are critical for product design and qualifications. We show that along with increased AFs and optimized product HTOL stress conditions, 5-10x more efficiency in time has been achieved. In addition, external mechanical strain on Fin reliability will be discussed.

DWT (discrete wavelet transform) based watermark system

In this paper a DWT (discrete wavelet transform) based watermarking system is proposed. The proposed embedding system changes coefficients. The extracting system rebuilds thresholds according to various attacks and decides a watermark bit from the least distorted coefficient. A new measure to detect the uniqueness of watermark is also proposed.

From WLR to product reliability and qualifications in the 3D transistor era

Reliability mechanisms associated with HK+MG transistors including latest FinFETs on 14nm technology node will be discussed along with circuit and product implications on reliabilty stresses and qualifications. Reliability efforts made at the transistor module level to circuit, IP blocks, and finally to a product level reliability will be discussed and limiting mechanisms and examples will be highlighted. As part of the product qual strategy, high-speed HTOL and Set level tests were leveraged to signficantly lower product dpms and seamless introduction of high volume manufacturing.