Sung-Woong Chung

Fully integrated 54nm STT-RAM with the smallest bit cell dimension for high density memory application

A compact STT(Spin-Transfer Torque)-RAM with a 14F2 cell was integrated using modified DRAM processes at the 54nm technology node. The basic switching performance (R-H and R-V) of the MTJs and current drivability of the access transistors were characterized at the single bit cell level. Through the direct access capability and normal chip operation in our STT-RAM test blocks, the switching behavior of bit cell arrays was also analyzed statistically. From this data and from the scaling trend of STT-RAM, we estimate that the unit cell dimension below 30nm can be smaller than 8F2.

Highly Scalable Saddle-Fin (S-Fin) Transistor for Sub-50nm DRAM Technology

Highly scalable saddle-fin cell transistor(S-Fin) has been successfully developed by combining FinFET with recess channel array transistor(RCAT). The S-Fin is simply integrated by dry-etching techniques and the desirable threshold voltage is easily obtained. The S-Fin exhibits feasible transistor characteristics such as excellent short channel effect, driving current, and refresh characteristics as compared with both RCAT and damascene-FinFET. We suggest the S-Fin is a very promising transistor structure for the sub-50nm DRAM technology

A Proposal on an Optimized Device Structure With Experimental Studies on Recent Devices for the DRAM Cell Transistor

We have experimentally analyzed the leakage mechanism and device degradations caused by the Fowler-Nordheim (F-N) and hot carrier stresses for the recently developed dynamic random-access memory cell transistors with deeply recessed channels. We have identified the important differences in the leakage mechanism between saddle fin (S-Fin) and recess channel array transistor (RCAT). These devices have their own respective structural benefits with regard to leakage current. Therefore, we suggest guidelines with respect to the optimal device structures such that they have the advantages of both S-Fin and RCAT structures. With these guidelines, we propose a new recess-FinFET structure that can be realized by feasible manufacturing process steps. The structure has the side-gate form only in the bottom channel region. This enhances the characteristics of the threshold voltage (VTH), ON/OFF currents, and the retention time distributions compared with the S-Fin structure introduced recently.

Integration of 4F2 selector-less crossbar array 2Mb ReRAM based on transition metal oxides for high density memory applications

4F2 selector-less crossbar array 2Mb ReRAM test chip with 54nm technology has been successfully integrated for high cell efficiency and high density memory applications by implementing parts of decoders to row/column lines directly under the cell area. Read/write specifications for memory operation in a chip are presented by minimizing sneak current through unselected cells. The characteristics of memory cell (nonlinearity, Kw >;8, Iop <;10uA, Vop<;60;3V), TiOx/Ta2O5, are modified for its working in a chip by adopting appropriate materials for a resistor stack and spacer. Write condition in a chip makes a critical impact on read margin and read/write operation in a chip has been verified.

Accurate analysis of conduction and resistive-switching mechanisms in double-layered resistive-switching memory devices

Resistive-switching and current conduction mechanisms have been studied in TiN/Ti/TiOx/HfOx/TiN resistive-switching random access memories (RRAMs). From I-V characteristics and temperature measurement, thermionic emission is found to be the most appropriate mechanism representing the dominant current conduction in all the bias regions and resistance states. Low-frequency noise power spectrum is measured to analyze accurately the conduction mechanism, which corroborates the thermionic-emission. Also, using the migration of oxygen ions depending on the polarity of the applied field, we propose the resistive-switching model of a double-layered RRAM to explain the unique resistive-switching characteristics.

Vertical double gate Z-RAM technology with remarkable low voltage operation for DRAM application

Vertical double gate floating body (FB) Z-RAM memory cell technology fabricated on a recess gate DRAM technology is presented. Cell operating voltage of 0.5V with comparable static retention and > 1000x improvement in dynamic retention is reported. The reported vertical double gate FB cell is the cell with the lowest operation voltage reported to date.

4Gbit density STT-MRAM using perpendicular MTJ realized with compact cell structure

For the first time, 4Gbit density STT-MRAM using perpendicular MTJ in compact cell was successfully demonstrated through the tight distributions for resistance and magnetic properties. This paper includes the results regarding parasitic resistance control process, MTJ process, and MTJ stack engineering. Both of successful 4Gb read and write operations were performed with high TMR, low Ic. This result will brighten the prospect of high-density STT-MRAM.

Extraction of trap location and energy from random telegraph noise in amorphous TiOx resistance random access memories

Random telegraph noise (RTN) has been studied in amorphous TiOx (α-TiOx) resistance switching random access memories (RRAMs). The RTN having two discrete current levels was observed only in the high-resistance state of the RRAMs. By investigating the bias dependence of capture and emission time constants, we extracted the vertical location of a trap responsible for the RTN in RRAM devices. The trap causing the RTN was found around 5.7 nm below the Ti (top electrode). The trap energy was less by 0.18 eV than the conduction band edge of the TiOx.

Spectroscopic study on resistive switching property of perovskite manganite film with controlled oxygen deficient state

La0.7Sr0.3MnO3 thin films were prepared on Pt/Ti/SiO2/Si substrates using a radio frequency magnetron sputtering technique under various Ar?:?O2 flow rates at a substrate temperature of 450??C. X-ray diffraction results showed that the growth orientation and crystallinity of film were affected by Ar?:?O2 ratio. Using x-ray photoelectron spectroscopy and near edge x-ray absorption fine structure, the chemical state of La0.7Sr0.3MnO3 film was revealed to have reduced oxygen deficiencies with increasing O2 flow during deposition. The valence band maximum was also shifted to the Fermi edge, and resistive switching properties were decreased with reduced oxygen vacancies from increased oxygen flow rate.

Comparative Study of Hydrido Organo Siloxane Polymer and Hydrogen Silsesquioxane.

Low-k candidate spin-on-glass (SOG) material hydrido organo siloxane polymer (HOSP) was evaluated and compared with flowable oxide (FOx). In particular, the chemical nature of the film and the effects of various processing steps on this chemical nature were investigated using Fourier transform infrared spectroscopy (FTIR), thermal desorption spectroscopy (TDS), a C–V meter and a stress gauge. The water absorption after various post-etch treatments was found to be a crucial factor affecting the dielectric properties of the film. HOSP proved to be a dielectric material with a lower k value than FOx and is more immune against moisture uptake. However, HOSP becomes more vulnerable to moisture absorption after oxygen plasma treatment. Electrical data from the process integration of HOSP were compared to those of FOx and conventional plasma-deposited oxide. The via resistance using HOSP was higher than that using the other materials. In particular, HOSP samples exhibited strong dependence on misalignment in resistance or leakage current measurements. The scanning electron microscope (SEM) image of these samples show that the electrical properties of HOSP samples resulted from a decrease in the actual via metal cross-section area due to via-poisoning.