Sung-Joo Hong

Novel 3-dimensional Dual Control-gate with Surrounding Floating-gate (DC-SF) NAND flash cell for 1Tb file storage application

A novel 3-dimensional Dual Control-gate with Surrounding Floating-gate (DC-SF) NAND flash cell has been successfully developed, for the first time. The DC-SF cell consists of a surrounding floating gate with stacked dual control gate. With this structure, high coupling ratio, low voltage cell operation (program: 15V and erase: −11V), and wide P/E window (9.2V) can be obtained. Moreover, negligible FG-FG interference (12mV/V) is achieved due to the control gate shield effect. Then we propose 3D DC-SF NAND flash cell as the most promising candidate for 1Tb and beyond with stacked multi bit FG cell (2 ∼ 4bit/cell).

A Proposal on an Optimized Device Structure With Experimental Studies on Recent Devices for the DRAM Cell Transistor

We have experimentally analyzed the leakage mechanism and device degradations caused by the Fowler-Nordheim (F-N) and hot carrier stresses for the recently developed dynamic random-access memory cell transistors with deeply recessed channels. We have identified the important differences in the leakage mechanism between saddle fin (S-Fin) and recess channel array transistor (RCAT). These devices have their own respective structural benefits with regard to leakage current. Therefore, we suggest guidelines with respect to the optimal device structures such that they have the advantages of both S-Fin and RCAT structures. With these guidelines, we propose a new recess-FinFET structure that can be realized by feasible manufacturing process steps. The structure has the side-gate form only in the bottom channel region. This enhances the characteristics of the threshold voltage (VTH), ON/OFF currents, and the retention time distributions compared with the S-Fin structure introduced recently.

25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV

Increasing demand for higher-bandwidth DRAM drive TSV technology development. With the capacity of fine-pitch wide I/O [1], DRAM can be directly integrated on the interposer or host chip and communicate with the memory controller. However, there are many limitations, such as reliability and testability, in developing the technology. It is advantageous to adopt a logic-interface chip between the interposer and stacked-DRAM with thousands of TSV. The logic interface chip in the base level of high-bandwidth memory (HBM) decreases the CIO, repairs the chip-to-chip connection failure, and supports better testability and improves reliability.

Memory technology trend and future challenges

Challenges in scaling semiconductor memory technologies are reviewed with special focus on DRAM and NAND Flash where technology scaling-down is at risk below 20nm. Some recent progress on overcoming scaling challenges of current and new memory technologies are introduced as well as some of the possible technology replacements are reviewed.

Integration of 4F2 selector-less crossbar array 2Mb ReRAM based on transition metal oxides for high density memory applications

4F2 selector-less crossbar array 2Mb ReRAM test chip with 54nm technology has been successfully integrated for high cell efficiency and high density memory applications by implementing parts of decoders to row/column lines directly under the cell area. Read/write specifications for memory operation in a chip are presented by minimizing sneak current through unselected cells. The characteristics of memory cell (nonlinearity, Kw >;8, Iop <;10uA, Vop<;60;3V), TiOx/Ta2O5, are modified for its working in a chip by adopting appropriate materials for a resistor stack and spacer. Write condition in a chip makes a critical impact on read margin and read/write operation in a chip has been verified.

A middle-1X nm NAND flash memory cell (M1X-NAND) with highly manufacturable integration technologies

A middle-1x nm design rule multi-level NAND flash memory cell (M1X-NAND) has been successfully developed for the first time. 1) QSPT (Quad Spacer Patterning Technology) of ArF immersion lithography is used for patterning mid-1x nm rule wordline (WL). In order to achieve high performance and reliability, several integration technologies are adopted, such as 2) advanced WL air-gap process, 3) floating gate slimming process, and 4) optimized junction formation scheme. And also, by using 5) new N±1 WL Vpass scheme during programming, charge loss and program speed are greatly improved. As a result, mid-1x nm design rule NAND flash memories has been successfully realized.

Accurate analysis of conduction and resistive-switching mechanisms in double-layered resistive-switching memory devices

Resistive-switching and current conduction mechanisms have been studied in TiN/Ti/TiOx/HfOx/TiN resistive-switching random access memories (RRAMs). From I-V characteristics and temperature measurement, thermionic emission is found to be the most appropriate mechanism representing the dominant current conduction in all the bias regions and resistance states. Low-frequency noise power spectrum is measured to analyze accurately the conduction mechanism, which corroborates the thermionic-emission. Also, using the migration of oxygen ions depending on the polarity of the applied field, we propose the resistive-switching model of a double-layered RRAM to explain the unique resistive-switching characteristics.

Vertical double gate Z-RAM technology with remarkable low voltage operation for DRAM application

Vertical double gate floating body (FB) Z-RAM memory cell technology fabricated on a recess gate DRAM technology is presented. Cell operating voltage of 0.5V with comparable static retention and > 1000x improvement in dynamic retention is reported. The reported vertical double gate FB cell is the cell with the lowest operation voltage reported to date.

Extraction of trap location and energy from random telegraph noise in amorphous TiOx resistance random access memories

Random telegraph noise (RTN) has been studied in amorphous TiOx (α-TiOx) resistance switching random access memories (RRAMs). The RTN having two discrete current levels was observed only in the high-resistance state of the RRAMs. By investigating the bias dependence of capture and emission time constants, we extracted the vertical location of a trap responsible for the RTN in RRAM devices. The trap causing the RTN was found around 5.7 nm below the Ti (top electrode). The trap energy was less by 0.18 eV than the conduction band edge of the TiOx.

Effect of oxygen migration and interface engineering on resistance switching behavior of reactive metal/polycrystalline Pr 0.7 Ca 0.3 MnO 3 device for nonvolatile memory applications

An in-depth study on the resistive switching mechanism of perovskite oxide based device was performed. Compared with filament type resistive switching device, excellent switching uniformity was obtained due to controlled redox reaction at metal/oxide interface. Electromigration of oxygen ion under the bipolar electric filed can explain the switching behavior. Formation of ultrathin AlOx at the interface can guarantee excellent retention characteristics at 125 °C. Compared with the large area (50 × 50 um2) memory cell, the nanoscale device (Φ=50 nm) showed better memory performance such as faster switching speed, better uniformity, endurance, and retention characteristics.