Sungho Lee

A CMOS Class-E Power Amplifier With Voltage Stress Relief and Enhanced Efficiency

This paper proposes a class-E power amplifier (PA) with double-resonance circuit to reduce voltage stress on CMOS transistors. The voltage waveform applied to the CMOS transistor is shaped by harmonic control and the transistors are relieved from breakdowns. A negative capacitance is also implemented for efficiency enhancement, compensating for surplus capacitance from parasitic components on the drain node. Thus, nominal class-E operation is restored and high efficiency is achieved. We present a cascode differential class-E RF PA that is fabricated using a 0.13-¿ m CMOS technology that delivers 31.5-dBm output power with 54% drain efficiency and 51% power-added efficiency at 1.8 GHz.

A CMOS dual-band fractional-n synthesizer with reference doubler and compensated charge pump

A fully integrated dual-band frequency synthesizer in 0.35 /spl mu/m CMOS technology achieves a phase noise of -141 dBc/Hz at 1.25 MHz offset in the PCS band with a reference frequency doubler. Fractional spurs are reduced by 8.6 dB at 50 kHz offset with a replica compensated charge pump.

Design of a 45

In this letter, a new type of resonant series slot array antenna for Ka-band for 45° linear polarization (LP) is described. Sixteen radiating slots, tilted at an angle of 45°, are separated by one-half guided wavelength due to use of the alternating inductive and capacitive load slot pairs. These alternating reactance slot pairs allow this novel antenna to achieve impedance matching, uniform field excitation, and suppression of grating lobes simultaneously. The antenna is designed and fabricated using substrate integrated waveguide (SIW) technology to overcome the drawbacks associated with conventional metallic waveguide antennas. The measured impedance bandwidth, maximum gain, and sidelobe levels are 2.7%, 15.64 dBi, and 15.36 dB, respectively, at the design frequency. The measured data are in agreement with the theoretical calculations and demonstrate the validity of the design technique for the proposed antenna structure.In this letter, a new type of resonant series slot array antenna for Ka-band for 45° linear polarization (LP) is described. Sixteen radiating slots, tilted at an angle of 45°, are separated by one-half guided wavelength due to use of the alternating inductive and capacitive load slot pairs. These alternating reactance slot pairs allow this novel antenna to achieve impedance matching, uniform field excitation, and suppression of grating lobes simultaneously. The antenna is designed and fabricated using substrate integrated waveguide (SIW) technology to overcome the drawbacks associated with conventional metallic waveguide antennas. The measured impedance bandwidth, maximum gain, and sidelobe levels are 2.7%, 15.64 dBi, and 15.36 dB, respectively, at the design frequency. The measured data are in agreement with the theoretical calculations and demonstrate the validity of the design technique for the proposed antenna structure.

Comparison frequency doubling and charge pump matching techniques for dual-band /spl Delta//spl Sigma/ fractional-N frequency synthesizer

The frequency synthesizer with two LC-VCOs is fully integrated in a 0.35-/spl mu/m CMOS technology. In supporting dual bands, all building blocks except VCOs are shared. A current compensation scheme using a replica charge pump improves the linearity of the frequency synthesizer and, thus, suppresses spurious tones. To reduce the quantization noise from a /spl Delta//spl Sigma/ modulator and the noise from the building blocks except the VCO, the proposed architecture uses a frequency doubler with a noise-insensitive duty-cycle correction circuit (DCC) in the reference clock path. Power consumption is 37.8 mW with a 2.7-V supply. The proposed frequency synthesizer supports 10-kHz channel spacing with the measured phase noise of -114 dBc/Hz and -141 dBc/Hz at 100-kHz and 1.25-MHz offsets, respectively, in the PCS band. The fractional spurious tone at 10-kHz offset is under -54 dBc.

A Design of a High-Speed and High-Efficiency Capsule Endoscopy System

This paper presents a high-speed and high-efficiency capsule endoscopy system. Both a transmitter and a receiver were optimized for its application through an analysis of the human body channel. ON-OFF keying modulation is utilized to achieve low power consumption of the in-body transmitter. A low drop output regulator is adopted to prevent performance degradation in the event of a voltage drop in the battery. The receiver adopts superheterodyne structure to obtain high sensitivity, considering the link budget from the previous analysis. The receiver and transmitter were fabricated using the CMOS 0.13-μm process. The output power of the transmitter is -1.6 dB·m and its efficiency is 27.7%. The minimum sensitivity of the receiver is -80 dB·m at a bit error ratio (BER) of 3 × 10 . An outer wall loop antenna is adopted for the capsule system to ensure a small size. The integrated system is evaluated using a liquid human phantom and a living pig, resulting in clean captured images.

A CMOS Outphasing Power Amplifier With Integrated Single-Ended Chireix Combiner

This brief proposes an on-chip outphasing power amplifier that uses a single-ended Chireix combiner for a linear amplification with a nonlinear component amplifier. The proposed combiner structure consists of a lumped inductor and a lumped capacitor that can achieve the simple single-ended configuration of a Chireix combiner. It is also suitable for on-chip implementation with minimum efficiency deterioration. An inductance-capacitance balun using the lumped model of λ/4 and 3λ/4 transmission lines was effectively merged into a simple Chireix combiner for two outphased input signals. The relation between the output resistance and the outphasing angle of the input signals was derived to determine the maximum efficiency. A voltage-mode class-D power amplifier was used with the combiner to illustrate the combiners effectiveness. The prototype fabricated in a 0.13-μm complementary metal-oxide-semiconductor process shows a maximum 52% power-added efficiency (continuous wave) and a -47-dBc adjacent channel power ratio performance at a 10-MHz offset with a 1.92-GHz wideband code-division multiple-access signal.

Self-Calibrated Two-Point Delta–Sigma Modulation Technique for RF Transmitters

A self-calibrated two-point delta-sigma modulation technique for CMOS RF transmitter is proposed. This calibration technique employs voltage-controlled oscillator (VCO) and delta-sigma modulator input ports in a frequency synthesizer. By monitoring the control voltage of a loop filter, the gain mismatch between two paths can be detected and completely calibrated by modifying the gain of the VCO path. The acceptable timing mismatch between the two paths is also investigated so that the timing can be controlled to ensure stable output performance. As a result, the phase modulation guarantees a robust performance against PVT variations without using any predistortion techniques. This technique is applied to a quad-band (850/900/1800/1900) GSM/EDGE transmitter for verification. For the amplitude modulation of the EDGE mode, a dc calibration is adopted to suppress unwanted carrier leakage tones. The measurement results show satisfactory GSM/EDGE spectrums and error vector magnitude performance at both low- and high-frequency bands.

Design of a 45

In this letter, a new type of resonant series slot array antenna for Ka-band for 45° linear polarization (LP) is described. Sixteen radiating slots, tilted at an angle of 45°, are separated by one-half guided wavelength due to use of the alternating inductive and capacitive load slot pairs. These alternating reactance slot pairs allow this novel antenna to achieve impedance matching, uniform field excitation, and suppression of grating lobes simultaneously. The antenna is designed and fabricated using substrate integrated waveguide (SIW) technology to overcome the drawbacks associated with conventional metallic waveguide antennas. The measured impedance bandwidth, maximum gain, and sidelobe levels are 2.7%, 15.64 dBi, and 15.36 dB, respectively, at the design frequency. The measured data are in agreement with the theoretical calculations and demonstrate the validity of the design technique for the proposed antenna structure.In this letter, a new type of resonant series slot array antenna for Ka-band for 45° linear polarization (LP) is described. Sixteen radiating slots, tilted at an angle of 45°, are separated by one-half guided wavelength due to use of the alternating inductive and capacitive load slot pairs. These alternating reactance slot pairs allow this novel antenna to achieve impedance matching, uniform field excitation, and suppression of grating lobes simultaneously. The antenna is designed and fabricated using substrate integrated waveguide (SIW) technology to overcome the drawbacks associated with conventional metallic waveguide antennas. The measured impedance bandwidth, maximum gain, and sidelobe levels are 2.7%, 15.64 dBi, and 15.36 dB, respectively, at the design frequency. The measured data are in agreement with the theoretical calculations and demonstrate the validity of the design technique for the proposed antenna structure.

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This paper presents the design and realization of wireless capsule endoscopy. For this system, the optimum frequency band is investigated to maximize the overall efficiency. To achieve low power consumption, a simple On-Off Keying (OOK) transmitter is utilized. To detect the transmitted signal from within the body, an external receiver adopted a superheterodyne structure and exhibited a sensitivity of −80dBm at BER 10−5. The system operates at up to 20Mbps. The OOK system is demonstrated in internally in a pigs body, showing clear internal body photos.

-Inclined SIW Resonant Series Slot Array Antenna for

A 500 MHz super-regenerative receiver (SRR) with a digitally self-quenching loop (DSQL) is designed for low-power/high-data-rate applications. The DSQL replaces the envelope detector used in a conventional SRR and minimizes the overall power consumption by generating a self-quench signal digitally for a super-regenerative oscillator. The receiver is fabricated using a 0.13 μm CMOS process. The chip size is 0.7 mm2 and the minimum energy usage is 0.09 nJ/b with a supply voltage of 1 V at a data rate of 10 Mbps. The measured sensitivity is - 76 dBm.