Kang-Yoon Lee

Secondary-Side LLC Resonant Controller IC With Dynamic PWM Dimming and Dual-Slope Clock Generator for LED Backlight Units

This paper presents a low-profile low-cost (LLC) resonant controller IC for LED backlight units fully operating at the secondary side. The integrated dimming circuitry is proposed to improve the dynamic current control characteristics and the LED current density for the brightness modulation of a large screen liquid crystal display. A dual-slope clock generator, including a soft start, is proposed in order to overcome the frequency error due to the undershoot found in conventional approaches. In addition, a new dead-time generator is proposed in order to implement an accurate dead time independent of the output frequency of the clock generator. Protection circuits, such as a under voltage lock out, thermal shut down, open LED detector, and shorted LED detector, have been implemented in order to improve the reliability of the controller IC. The chip is fabricated using 0.35 μm bipolar CMOS DMOS decimal technology; the die size is 2 mm × 2 mm. The frequency of the clock generator ranges from 50 to 500 kHz; the dead time ranges from 50 ns to 2.2 μs. The efficiency of the LED driving circuit is 91%. The current consumption of the LLC resonant controller IC is 40 mA for a 100 kHz operation frequency using a 15 V supply voltage.

Self-Calibrated Two-Point Delta–Sigma Modulation Technique for RF Transmitters

A self-calibrated two-point delta-sigma modulation technique for CMOS RF transmitter is proposed. This calibration technique employs voltage-controlled oscillator (VCO) and delta-sigma modulator input ports in a frequency synthesizer. By monitoring the control voltage of a loop filter, the gain mismatch between two paths can be detected and completely calibrated by modifying the gain of the VCO path. The acceptable timing mismatch between the two paths is also investigated so that the timing can be controlled to ensure stable output performance. As a result, the phase modulation guarantees a robust performance against PVT variations without using any predistortion techniques. This technique is applied to a quad-band (850/900/1800/1900) GSM/EDGE transmitter for verification. For the amplitude modulation of the EDGE mode, a dc calibration is adopted to suppress unwanted carrier leakage tones. The measurement results show satisfactory GSM/EDGE spectrums and error vector magnitude performance at both low- and high-frequency bands.

An

A dual-mode RF receiver with low-IF architecture has been developed for L1-band Global Positioning System (GPS) and Galileo system in a 0.18- mum CMOS process. The channel-selecting bandpass filter centered at 4.092 MHz has programmable bandwidth (2.046 MHz, 4.092 MHz), which allows the reception of GPS and Galileo signals. A fractional-N phase-locked loop generates the local oscillator signals, which allows multiple reference clock frequencies, and in turn, share of a reference oscillator with other systems. The noise figure of the receiver is 4.5 dB, while consuming 41.4 mW from a 1.8-V supply. The image signal is rejected by more than 34 dB.

L1

In this paper, class-E power amplifier (PA) with automatic power control loop and load compensation circuit is presented. The transmitted power is controlled by adjusting the signal applied to the gate of the power control transistor. In addition, a parallel capacitor is also controlled to enhance the efficiency and compensate for the load variation. This chip is implemented in a 0.35 µm BCD technology, and provides the output power control range of 10–30.2 dBm. The maximum power efficiency of the power amplifier is 71.5 %.

-Band Dual-Mode RF Receiver for GPS and Galileo in 0.18-

In this paper, the transceiver for RFID reader using 13.56MHz as a carrier frequency and meeting International Standard ISO 14443 type A, 14443 type B and 15693 is presented. The receiver is composed of envelope detector, VGA (Variable Gain Amplifier), low pass filter, limiter, and comparator to recovery the received signal. The proposed automatic reference voltage generator can adjust the decision level of reference voltage over the received signal amplitudes. Also, the limiter can reduce the initial settling time that affects the data latency. The transmitter is designed to meet 15693 specification. By using inductor loading circuit which can swing more than power supply and make large current even under low impedance condition, it can control modulation index from 5 % to 100 %t and output currents from 5 mA to 240 mA in respect of each standard. The 13.56 MHz RFID reader is implemented in 0.18 μm CMOS technology at 3.3 V single supply. The chip area excluding pads is 1.5 mm × 1.5 mm

\mu {\hbox{m}}

Recently, the investigation of the cognitive radio (CR) system is actively progressed as one of the methods for using the frequency resources more efficiently. In CR systems, when the frequency band allocated to the incumbent user is not used, the unused frequency band is assigned to the secondary user. Thus, the FFT input signals corresponding to the actually used frequency band by the incumbent user are assigned as ‘0’. In this paper, based on the fact that there are many ‘0’ input signals in CR systems, a low-power FFT design method for NC-OFDM is proposed. An efficient zero flag generation technique for each stage is first presented. Then, to increase the utility of the zero flag signals, modified architectures for memory and arithmetic circuits are presented. To verify the performance of the proposed algorithm, 2048 point FFT with radix-24 SDF structure is designed using Verilog HDL. The simulation results show that the power consumption of FFT is reduced considerably by the proposed algorithm.

CMOS

Subcritical water extract (SWE) of Brassica juncea was studied for antiviral effects against influenza virus A/H1N1 and for the possibility of application as a nonfat milk supplement for use as an antiviral food. At maximum nontoxic concentrations, SWE had higher antiviral activity against influenza virus A/H1N1 than n-hexane, ethanol, or hot water (80°C) extracts. Addition of 0.5mg/mL of B. juncea SWE to culture medium led to 50.35% cell viability (% antiviral activity) for Madin-Darby canine kidney cells infected with influenza virus A/H1N1. Nonfat milk supplemented with 0.28mg/mL of B. juncea SWE showed 39.62% antiviral activity against influenza virus A/H1N1. Thus, the use of B. juncea SWE as a food supplement might aid in protection from influenza viral infection.

A design of high efficiency class-E power amplifier for wireless power transfer system

In this paper, a mode matching control loop is suggested for the matching of the resonant frequency of the sensing mode with that of the driving mode. Matching of two modes is critical issue of the MEMS vibratory gyroscope to achieve the high sensitivity of the sensor. A new mode matching control loop using the concept of phase locked loop (PLL) is proposed and analyzed. Through the computer simulation using MATLAB and experiments using a real MEMS gyroscope, it is verified that the proposed control loop design matches those two modes and correspondingly improves the sensitivity of a gyroscope.

A design of transceiver for 13.56 MHz RFID reader using the peak detector with automatic reference voltage generator and voltage limiter

This paper presents a baseband complex bandpass filter for PHS applications with a new automatic tuning method. The full-CMOS PHS transceiver is implemented by adopting the Low-IF architecture to overcome the DC-offset problems. To meet the adjacent channel selectivity (ACS) performance, the 3rd-order Chebyshev complex bandpass filter is designed as the baseband channel-select filter. The new corner frequency tuning method is proposed to compensate the process variation. This method can reduce the noise level due to MOS switches. The filter was fabricated using a 0.35 mum CMOS process, and the power consumption is 12 mW.

Low-power FFT design for NC-OFDM in cognitive radio systems

This paper describes a 3 to 5 GHz frequency synthesizer for MB-OFDM (multi-band OFDM) UWB (Ultra-Wideband) application using 0.13 um CMOS process. The frequency synthesizer operates in the band group 1 whose center frequencies are 3432 MHz, 3960 MHz, and 4488 MHz. To cover the overall frequencies of group 1, an efficient frequency planning minimizing a number of blocks and the power consumption are proposed. And, a high-frequency VCO and prescaler architecture are also presented in this paper. A new coarse tuning scheme that utilizes the MIM capacitance and the varactor is proposed to expand the VCO tuning range. The single PLL and two SSB-mixers consume 75 mW from a 1.5 V supply. The VCO tuning range is 500 MHz. The simulated phase noise of the VCO is -110 dBc/Hz at 1 MHz offset. The die area is 3 x 2 mm2.