Sunghwan Park

Broadband CMOS stacked power amplifier using reconfigurable interstage network for envelope tracking application

A 2-stage stacked-FET power amplifier with a reconfigurable interstage network is developed for broadband envelope tracking application using SOI CMOS. The wideband PA is based on Class-J mode of operation, where output matching is realized with two-section low-pass network. Miller capacitors are also employed across the FET stack to guarantee Class-J-like operation for inner FET stacks. To overcome the bandwidth limit due to high-Q interstage matching, reconfigurable matching network is employed using SOI switch, allowing dual frequency-mode operation. The fabricated PA shows CW efficiencies in excess of 60% from 0.65 to 1.0 GHz. When operated with an ET supply modulator, overall ET PA system shows W-CDMA efficiencies higher than 50% from 0.68 to 0.92 GHz and LTE efficiencies higher than 40% from 0.65 to 0.95 GHz.

Broadband CMOS Stacked RF Power Amplifier Using Reconfigurable Interstage Network for Wideband Envelope Tracking

In this paper, a two-stage broadband CMOS stacked FET RF power amplifier (PA) with a reconfigurable interstage matching network is developed for wideband envelope tracking (ET). The proposed RF PA is designed based on Class-J mode of operation, where the output matching is realized with a two-section low-pass matching network. To overcome the bandwidth (BW) limitation from the high- Q interstage impedance, a reconfigurable matching network is proposed, allowing a triple frequency mode of operation using two RF switches. The proposed RF PA is fabricated in a 0.32- μm silicon-on-insulator CMOS process and shows continuous wave (CW) power-added efficiencies (PAEs) higher than 60% from 0.65 to 1.03 GHz with a peak PAE of 69.2% at 0.85 GHz. The complete ET PA system performance is demonstrated using the envelope amplifier fabricated on the same process. When measured using a 20-MHz BW long-term evolution signal, the overall system PAE of the ET PA is higher than 40% from 0.65 to 0.97 GHz while evolved universal terrestrial radio access adjacent channel leakage ratios are better than -33 dBc across the entire BW after memoryless digital pre-distortion. To our knowledge, this study represents the highest overall system performance in terms of PAE and BW among the published broadband ET PAs, including GaAs HBT and SiGe BiCMOS.

Dynamic Stack-Controlled CMOS RF Power Amplifier for Wideband Envelope Tracking

In this paper, a dynamic stack-controlled CMOS FET RF power amplifier (PA) is developed to enhance the efficiency of the envelope tracking power amplifier (ET PA) system for low-voltage operation. The power cell used in the two-stage PA is a quadruple-stacked FET structure with dynamic stacking controller to reconfigure the power cell into the quasi-triple or quasi-double stacks according to the magnitude of the input envelope signal. The proposed power cell boosts the peak efficiency in the low VDD region by bypassing the stack entering the triode region and reoptimizing the load impedance so that all the FETs operate under the saturation and the optimum load conditions. A detailed analysis is presented to understand the gain and phase step discontinuities at the stack switching points, and the circuit techniques to equalize the gain and phase between the adjacent stack configurations are developed. The proposed two-stage stack-controlled PA is fabricated with a 0.32-μm silicon-on-insulator (SOI) CMOS process together with the envelope amplifier (EA). Full long-term evolution (LTE) characterization is performed using LTE signals with a peak-to-average power ratio (PAPR) of 6.7 dB and signal bandwidths (BW) of 10 and 20 MHz. With 10-MHz signals, dynamic stacking provides 3.5% power added efficiency (PAE) improvement over the static stack at 25.7 dBm, resulting in 47.5% PAE with 26.6-dB gain. A 20-MHz LTE test shows an overall PAE of 45.9% with an evolved universal terrestrial radio access (E-UTRA) adjacent channel leakage ratio (ACLR) of -33 dBc with memoryless digital predistortion. Even with the lower efficiency of the EA compared with the state-of-the-art results, the measured overall system efficiency with 3.4 V maximum voltage is comparable with those reported using GaAs HBTs with 5 V supplies, which clearly demonstrates the advantages of the proposed dynamic stack control.

A single-chain multiband reconfigurable linear power amplifier in SOI CMOS

A multiband linear CMOS power amplifier (PA) is developed to cover multiple LTE bands from 800 to 2000 MHz using a single PA core. The single-chain PA is based on a two-stage design using stacked-FET cells, and is designed to support any combinations of low/high dual bands out of five popular 3G/4G bands (Band 1/2/4/5/8). To avoid the performance degradation by covering such a wide bandwidth using a single PA-core, the frequency reconfigurability has been applied to the stacked-FET cells, interstage matching as well as the output matching. To further enhance the linearity and efficiency, a phase-based linearizer is employed and reconfigured according to the operating frequencies. W-CDMA test on the fabricated PA shows adjacent channel leakage ratios (ACLRs) better than -39 dBc up to the rated linear power of 28.5 dBm and power-added efficiencies (PAEs) higher than 40.7% and 46% for high- and low- frequency band groups, respectively. Compared with the dedicated PAs using the same process, PAE degradation is limited to 1.6 ~ 3.3%. To our knowledge, this work is among the best results from the single-chain PAs for 3G/4G mobile applications.

A CMOS Stacked-FET Power Amplifier Using PMOS Linearizer with Improved AM-PM

A linear stacked field-effect transistor (FET) power amplifier (PA) is implemented using a 0.18-μm silicon-on-insulator CMOS process for W-CDMA handset applications. Phase distortion by the nonlinear gate-source capacitance (Cgs) of the common-source transistor, which is one of the major nonlinear sources for intermodulation distortion, is compensated by employing a PMOS linearizer with improved AM-PM. The linearizer is used at the gate of the driver-stage instead of main-stage transistor, thereby avoiding excessive capacitance loading while compensating the AM-PM distortions of both stages. The fabricated 836.5 MHz linear PA module shows an adjacent channel leakage ratio better than —40 dBc up to the rated linear output power of 27.1 dBm, and power-added efficiency of 45.6% at 27.1 dBm without digital pre-distortion.

A wideband envelope-tracking CMOS linear transmitter without digital predistortion

In this work, an effective linearization technique to linearize both AM-PM and AM-AM distortions in CMOS envelope tracking (ET) transmitter is developed using dual shaping tables. AM-AM response is linearized using iso-gain shaping table. A variable phase shifter is integrated with the RF power amplifier (RF PA), which linearizes AM-PM response of CMOS ET PA in conjunction with the iso-gain shaping table. In this way, no additional digital predistortion (DPD) is required to linearize the CMOS ET PA. The 2-stage RF PA with the integrated phase compensation circuit is fabricated in 0.28-μm SOI CMOS process. The ET transmitter system demonstrated using the CMOS envelope amplifier (EA) shows an overall system PAE of 42.2% with -34.5 dBc E-UTRA ACLR with 40 MHz BW LTE signal centered at 0.837 GHz. The proposed method overcomes the bandwidth limitation of the conventional methods relying on DPD and/or feedback loops, and can be applied to wide bandwidth LTE signals.

A Pulsed Dynamic Load Modulation Technique for High-Efficiency Linear Transmitters

A pulsed dynamic load modulation (PDLM) technique is introduced for a high-efficiency linear transmitter for wideband modulation signals with a large peak-to-average power ratio. By combining the dynamic load modulation technique with the class-S amplifier concept, the pulse-width-modulated envelope signal is applied to the switchable-load matching circuit so that the power amplifier (PA) can operate near optimum efficiencies in the backed-off power region. A comprehensive analysis is presented to prove the circuit concept using the simplified theory, followed by the full circuit simulations using harmonic-balance analysis. The effect of nonideal terminations at the intrinsic device plane is also analyzed to understand the potential issues in the practical implementation. The proof-of-concept circuits are designed and fabricated using a silicon-on-insulator CMOS process, where a two-stage PA, a load switch, a pulse-width modulation circuit, and a switch driver are implemented in two separate chips. The fabricated PDLM PA operating at 837 MHz shows continuous-wave efficiencies in excess of 44% across the 6-dB power back-off region from the saturated output power. A power-added efficiency as high as 43.4% is achieved at the output power of 24.8 dBm using 10-MHz-bandwidth 16 quadrature amplitude modulation long-term evolution (LTE) signals. Unlike the case of the envelope-tracking techniques, the PDLM PA of this work maintains the overall efficiencies as the LTE signal bandwidth increases. The PDLM PA of this work can provide a potential solution for high-efficiency PAs for future mobile terminals using wideband modulation signals.

A 5.7 GHz GaN transformer-based Doherty Power Amplifier for 40-MHz LTE-A applications

In this work, a hybrid 5.7 GHz gallium-nitride high electron mobility transistor (GaN HEMT) transformer-based Doherty power amplifier (TBD PA) to support 40-MHz bandwidth (BW) long term evolution-advanced (LTE-A) applications is presented. A series-combining transformer is used to realize Doherty action instead of using conventional quarter-wave length impedance inverter to cover wide bandwidth modulation signals. Also the AM-PM distortion generated by the Doherty action is compensated with a varactor-based linearizer to gain better linearity. The proposed hybrid TBD PA is implemented using Crees 6 W GaN HEMT bare die (CGHV1J006) and Semcos 7 layer PCB. The TBD PA is tested at 5.7 GHz carrier frequency and showing 43% peak PAE and 39.3 dBm maximum output power with continuous wave (CW) signal, −33 dBc CA E-UTRAACLR at 31.8 dBm output power with 40-MHz BW LTE-A Signal by using the fabricated linearizer.

A Highly Efficient Dual-Mode 3G/4G Linear CMOS Stacked-FET Power Amplifier Using Active-Bypass

A highly efficient dual-mode linear CMOS stacked-FET power amplifier (PA) is implemented for 3G UMTS and 4G LTE handset applications. High efficiency is achieved at a backed-off output power (P out ) below 12 dBm by employing an active-bypass amplifier, which consumes very low quiescent current and has high load-impedance. The output paths between high-and low-power modes of the PA are effectively isolated by using a bypass switch, thus no RF performance degradation occurs at high-power mode operation. The fabricated 900 MHz CMOS PA using silicon-on-insulator(SOI) CMOS process operates with an idel current of 5.5 mA and show power-added efficiency (PAE) of 20.5%/43.5% at P out = 12.4/28.2dBm while maintaining an adjacent channel leakage ratio (ACLR) better than -39dBc, using the 3GPP uplink W-CDMA signal. The PA also exhibits PAE of 35.1% and ACLR E-UTRA of-33 dBc at P out = 26.5 dBm, using the 20 MHz bandwidth 16-QAM LTE signal.

A Highly Efficient Multi-Mode Balanced Power Amplifier for W-CDMA Handset Applications

A highly efficient multi-mode balanced power amplifier(PA) structure is proposed for W-CDMA handset applications. The proposed PA has 2-stage amplifier configuration and the stage-bypass and load impedance switching techniques were applied to enhance power efficiency at medium power level as well as low output power level. Using the two techniques, four highly efficient power modes were realized. To demonstrate the usefulness of the proposed structure, a GaAs HBT balanced PA module was designed, fabricated, and measured.