Unha Kim

A new "series-type" Doherty amplifier for miniaturization

A new topology of Doherty amplifier is proposed to reduce the circuit size by eliminating the bulky 3 dB 90/spl deg/ hybrid coupler. Unlike the classical Doherty amplifier, the carrier and peak amplifiers are connected in series together with an impedance-inverting network connecting the outputs of both amplifiers. A simple matching circuit between the peak and carrier amplifier replaces the input hybrid coupler. In this way, the need for an input hybrid coupler is eliminated, facilitating integration and miniaturization. The fabricated 2.45 GHz amplifier module using the proposed topology demonstrates enhanced efficiencies in the low- to mid-power ranges and shows good gain flatness. This approach is promising for highly-integrated Doherty-type amplifiers for handset applications.

Broadband CMOS stacked power amplifier using reconfigurable interstage network for envelope tracking application

A 2-stage stacked-FET power amplifier with a reconfigurable interstage network is developed for broadband envelope tracking application using SOI CMOS. The wideband PA is based on Class-J mode of operation, where output matching is realized with two-section low-pass network. Miller capacitors are also employed across the FET stack to guarantee Class-J-like operation for inner FET stacks. To overcome the bandwidth limit due to high-Q interstage matching, reconfigurable matching network is employed using SOI switch, allowing dual frequency-mode operation. The fabricated PA shows CW efficiencies in excess of 60% from 0.65 to 1.0 GHz. When operated with an ET supply modulator, overall ET PA system shows W-CDMA efficiencies higher than 50% from 0.68 to 0.92 GHz and LTE efficiencies higher than 40% from 0.65 to 0.95 GHz.

Broadband CMOS Stacked RF Power Amplifier Using Reconfigurable Interstage Network for Wideband Envelope Tracking

In this paper, a two-stage broadband CMOS stacked FET RF power amplifier (PA) with a reconfigurable interstage matching network is developed for wideband envelope tracking (ET). The proposed RF PA is designed based on Class-J mode of operation, where the output matching is realized with a two-section low-pass matching network. To overcome the bandwidth (BW) limitation from the high- Q interstage impedance, a reconfigurable matching network is proposed, allowing a triple frequency mode of operation using two RF switches. The proposed RF PA is fabricated in a 0.32- μm silicon-on-insulator CMOS process and shows continuous wave (CW) power-added efficiencies (PAEs) higher than 60% from 0.65 to 1.03 GHz with a peak PAE of 69.2% at 0.85 GHz. The complete ET PA system performance is demonstrated using the envelope amplifier fabricated on the same process. When measured using a 20-MHz BW long-term evolution signal, the overall system PAE of the ET PA is higher than 40% from 0.65 to 0.97 GHz while evolved universal terrestrial radio access adjacent channel leakage ratios are better than -33 dBc across the entire BW after memoryless digital pre-distortion. To our knowledge, this study represents the highest overall system performance in terms of PAE and BW among the published broadband ET PAs, including GaAs HBT and SiGe BiCMOS.

Dynamic Stack-Controlled CMOS RF Power Amplifier for Wideband Envelope Tracking

In this paper, a dynamic stack-controlled CMOS FET RF power amplifier (PA) is developed to enhance the efficiency of the envelope tracking power amplifier (ET PA) system for low-voltage operation. The power cell used in the two-stage PA is a quadruple-stacked FET structure with dynamic stacking controller to reconfigure the power cell into the quasi-triple or quasi-double stacks according to the magnitude of the input envelope signal. The proposed power cell boosts the peak efficiency in the low VDD region by bypassing the stack entering the triode region and reoptimizing the load impedance so that all the FETs operate under the saturation and the optimum load conditions. A detailed analysis is presented to understand the gain and phase step discontinuities at the stack switching points, and the circuit techniques to equalize the gain and phase between the adjacent stack configurations are developed. The proposed two-stage stack-controlled PA is fabricated with a 0.32-μm silicon-on-insulator (SOI) CMOS process together with the envelope amplifier (EA). Full long-term evolution (LTE) characterization is performed using LTE signals with a peak-to-average power ratio (PAPR) of 6.7 dB and signal bandwidths (BW) of 10 and 20 MHz. With 10-MHz signals, dynamic stacking provides 3.5% power added efficiency (PAE) improvement over the static stack at 25.7 dBm, resulting in 47.5% PAE with 26.6-dB gain. A 20-MHz LTE test shows an overall PAE of 45.9% with an evolved universal terrestrial radio access (E-UTRA) adjacent channel leakage ratio (ACLR) of -33 dBc with memoryless digital predistortion. Even with the lower efficiency of the EA compared with the state-of-the-art results, the measured overall system efficiency with 3.4 V maximum voltage is comparable with those reported using GaAs HBTs with 5 V supplies, which clearly demonstrates the advantages of the proposed dynamic stack control.

A Multi-Mode Multi-Band Reconfigurable Power Amplifier for 2G/3G/4G Handset Applications

Fully-integrated multi-mode multi-band (MMMB) reconfigurable power amplifier (PA) is implemented using single PA-cores for high- and low-frequency bands, respectively. This PA has five output paths and covers quad-band Gaussian Minimum Shift Keying/Enhanced Data Rates for Global Evolution and penta-band Universal Mobile Telecommunications System/Long Term Evolution mode operation with band combination in a small form-factor. To optimize the PA, the proposed structure reconfigures the PA-core cells as well as the interstage/output matching network. When compared with the single-mode single-band dedicated PAs, the fabricated PA showed comparable RF performance for all modes and bands, except for PAE degradations of 3.1% and 1.9% for high- and low-band, respectively, thus validating the usefulness of the proposed structure for MMMB PA applications.

A multi-mode multi-band reconfigurable power amplifier for low band GSM/UMTS handset applications

A practical reconfigurable structure for multi-mode multi-band (MMMB) reconfigurable power amplifier (PA) is proposed for GSM/UMTS handset applications. To overcome not only the frequency difference (MB) but also the power difference (MM) between GSM and UMTS standards, the proposed structure reconfigures the PA core as well as the output matching network. To verify the performance of the proposed structure, a MMMB PA is developed for GSM/EDGE/UMTS low-frequency bands applications. The fabricated MMMB PA showed good RF performance for UMTS as well as GSM/EDGE applications. Efficiency degradation was limited to less than 2% compared to the single-mode single-band PA. Measured RF performance validates the usefulness of the proposed structure for MMMB applications.

A Programmable Impedance Tuner With Finite SWRs for Load-Pull Measurement of Handset Power Amplifiers

A novel coupler/reflection-type electronic impedance tuner is proposed with quantitative analysis. The tuner is divided into a magnitude part and a phase part, and the magnitude and phase of the tuner impedance can be controlled separately just with one design parameter, respectively, thus facilitating programmable control for constant magnitude and uniform phase distribution. The tuner with standing wave ratio (SWR) = 2.5 and 6 was implemented for 3G/4G handset low-band transmitter (Tx) power amplifier (PA) load-pull measurement. The fabricated tuner showed very uniform reflection coefficient distribution with magnitude deviations of less than 0.05/0.08 at SWR = 2.5 / 6 and phase deviations of less than 5 °. PA load-pull measurement result using the tuner showed good agreement with a mechanical tuner, thus verifying the practical usefulness of the proposed tuner.

A Linearity-Enhanced Compact Series-Type Doherty Amplifier Suitable for CDMA Handset Applications

A high-linearity series-type Doherty amplifier that does not use bulky 3 dB quadrature hybrid coupler is developed for mobile handset applications. A predistorter is employed at the input to improve the ACPR performance at the high-power region, which effectively extends maximum linear power range. For size and stability considerations, the phasing circuits between the carrier and peak amplifiers have been realized using high-pass T-networks. The series-type Doherty amplifier of this work shows PAEs of 18% and 42.8% at 16 dBm and 28 dBm, while meeting the IS-95A ACPR requirement of -42 dBc

A High-Efficiency SOI CMOS Stacked-FET Power Amplifier Using Phase-Based Linearization

A linearization technique based on the phase correction is proposed for a CMOS stacked-FET power amplifier (PA). The linearizer employs a phase injection circuit as a main linearizer. The phase injection circuit presents envelope-reshaped capacitance to the gate of a driver amplifier to correct for phase compression near saturation. It also helps with AM-AM linearization. Hybrid bias circuit consisting of a diode and a resistor is also employed for static adaptive biasing, which allows the PA to meet stringent linearity requirement across the entire power range. Two stacked-FET linear PAs with the proposed linearizers have been designed using a silicon-on-insulator (SOI) CMOS process at 1.88 and 0.9 GHz. The fabricated PAs show adjacent channel leakage ratios (ACLRs) better than -39 dBc with peak power-added efficiencies (PAEs) of 44.3 and 49.2% at 1.88 and 0.9 GHz, respectively, using 3GPP uplink W-CDMA signal.

A single-chain multiband reconfigurable linear power amplifier in SOI CMOS

A multiband linear CMOS power amplifier (PA) is developed to cover multiple LTE bands from 800 to 2000 MHz using a single PA core. The single-chain PA is based on a two-stage design using stacked-FET cells, and is designed to support any combinations of low/high dual bands out of five popular 3G/4G bands (Band 1/2/4/5/8). To avoid the performance degradation by covering such a wide bandwidth using a single PA-core, the frequency reconfigurability has been applied to the stacked-FET cells, interstage matching as well as the output matching. To further enhance the linearity and efficiency, a phase-based linearizer is employed and reconfigured according to the operating frequencies. W-CDMA test on the fabricated PA shows adjacent channel leakage ratios (ACLRs) better than -39 dBc up to the rated linear power of 28.5 dBm and power-added efficiencies (PAEs) higher than 40.7% and 46% for high- and low- frequency band groups, respectively. Compared with the dedicated PAs using the same process, PAE degradation is limited to 1.6 ~ 3.3%. To our knowledge, this work is among the best results from the single-chain PAs for 3G/4G mobile applications.