Sungju Choi

A Study on the Degradation of In-Ga–Zn-O Thin-Film Transistors Under Current Stress by Local Variations in Density of States and Trapped Charge Distribution

Thin-film transistors using In-Ga-Zn-O (IGZO) semiconductors were evaluated under current stress by applying positive voltages to the gate and drain electrodes. Initially, the transfer characteristics exhibit identical threshold voltages (VT) when the source and drain electrodes are interchanged during measurement (forward and reverse VDS sweep). However, as stress time increases, larger shifts in VT are observed under forward VDS sweep than under reverse VDS sweep conditions. Subgap states analyses based on the photoresponse of capacitance-voltage (C-V) curves suggest that local annihilation of donor-like traps occurs near the drain electrode. Hump-like features are clearly observed in the C-V curves collected between the drain and gate electrodes, while they do not appear in the C-V data obtained between the source and the gate. Based on the above, a local charge trapping model is introduced in order to interpret the device degradation. In this model, the major carrier electrons are trapped more abundantly near the source electrode due to the presence of a Schottky junction between IGZO and the source/drain electrodes.

Modeling and Characterization of the Abnormal Hump in n-Channel Amorphous-InGaZnO Thin-Film Transistors After High Positive Bias Stress

Hump characteristics of n-channel amorphous indium-gallium-zinc-oxide (a-InGaZnO) thin-film transistors (TFTs) after positive gate and drain bias stress (PGDBS) are investigated. With the increase of the PGDBS time, we observed not only a shift of the threshold voltage (V_T) but also a generation of the hump in the transfer characteristics. The hump is caused by the localized trapping of electrons in the gate insulator over the gate-source overlap region by the high vertical field during the PGDBS (V_GS = 30, V_DS = 30; V_GD = V_GS - V_DS = 0 V). The TFT with a hump after PGDBS is modeled as a series connection of main and parasitic TFTs. The parasitic TFT for the electron trapping at the gate-source overlap region has a higher threshold voltage (V_Tp) and a shorter effective channel length (L_chp ≅ Lov) compared with those (V_Tm and L_ch) of the main TFT.

Evaluation of interface trap densities and quantum capacitance in carbon nanotube network thin-film transistors.

The interface trap density in single-walled carbon nanotube (SWNT) network thin-film transistors (TFTs) is a fundamental and important parameter for assessing the electronic performance of TFTs. However, the number of studies on the extraction of interface trap densities, particularly in SWNT TFTs, has been insufficient. In this work, we propose an efficient technique for extracting the energy-dependent interface traps in SWNT TFTs. From the measured dispersive, frequency-dependent capacitance-voltage (C-V) characteristics, the dispersive-free, frequency-independent C-V curve was obtained, thus enabling the extraction and analysis of the interface trap density, which was found to be approximately 8.2 × 10(11) eV(-1) cm(-2) at the valence band edge. The frequency-independent C-V curve also allows further extraction of the quantum capacitance in the SWNT network without introducing any additional fitting process or parameters. We found that the extracted value of the quantum capacitance in SWNT networks is lower than the theoretical value in aligned SWNTs due to the cross point of SWNTs on the SWNT network. Therefore, the method proposed in this work indicates that the C-V measurement is a powerful tool for obtaining deep physical insights regarding the electrical performance of SWNT TFTs.

Frequency-dependent C-V Characteristic-based Extraction of Interface Trap Density in Normally-off Gate-recessed AlGaN/GaN Heterojunction Field-effect Transistors

It is essential to acquire an accurate and simple technique for extracting the interface trap density (Dit) in order to characterize the normally-off gate-recessed AlGaN/GaN hetero field-effect transistors (HFETs) because they can undergo interface trap generation induced by the etch damage in each interfacial layer provoking the degradation of device performance as well as serious instability. Here, the frequency-dependent capacitance-voltage (C-V) method (FDCM) is proposed as a simple and fast technique for extracting Dit and demonstrated in normally-off gate-recessed AlGaN/GaN HFETs. The FDCM is found to be not only simpler than the conductance method along with the same precision, but also much useful for a simple C-V model for AlGaN/GaN HFETs because it identifies frequency-independent and bias- dependent capacitance components.

The Effect of Gate and Drain Fields on the Competition Between Donor-Like State Creation and Local Electron Trapping in In–Ga–Zn–O Thin Film Transistors Under Current Stress

Thin-film transistors using In-Ga-Zn-O (IGZO) semiconductors were evaluated under positive bias stress with different gate and drain voltages (VGS and VDS, respectively). The transfer characteristics with respect to stress time were examined, focusing on the threshold voltage (VT) values obtained when the source and drain electrodes are interchanged during readout (forward and reverse VDS sweep). The VT values shift toward either negative or positive values during stress, while transitions from negative to positive shifts are also observed. The negative VT shift under positive bias stress is interpreted to occur by the generation of donor-like states related to ionized oxygen vacancies. On the other hand, positive VT shifts result from the trapping of electrons near the IGZO/gate insulator interface. The transitions from negative to positive VT shift are believed to result from the local electron trapping mechanism that gradually takes over donor-like state creation. From the experimental results and TCAD device simulation, it is suggested that a competition occurs between donor-like state creation and electron trapping. The relative magnitudes of the VGS and VDS fields determine which mechanism dominates, providing an analytical insight for the design of stable devices for driving transistors in AMOLED backplanes.

Comprehensive separate extraction of parasitic resistances in MOSFETs considering the gate bias-dependence and the asymmetric overlap length

Abstract Parasitic resistances cause degradation of transconductance (gm), cutoff frequency (fT), current driving capability, and long term reliability of MOSFETs. We report a comprehensive extraction of parasitic resistance components in MOSFETs for the contact, the spreading current path, and the lightly doped drain region caused by the process, structure, and degradation. We considered the gate bias (VGS)-dependence and the asymmetric overlap length (Lov,SD) in the source and drain. We report systematically integrated extraction technique combined with the channel resistance method, the transfer length method, the dual-sweep combinational transconductance technique, the open drain method, and the parasitic junction current method. VGS-independent resistances were separated to be RSe = 6.8–6.9 Ω, RDe = 7.4–7.5 Ω, RSUB = 7.4–7.6 Ω, RSo = 1.8–2.1 Ω, and RDo = 3.2–3.5 Ω for MOSFETs with and at W/L = 50 μm/0.27 μm. VGS-dependent intrinsic resistances are obtained to be RSi = 1.9–4.4 Ω, RDi = 1.4–3.2 Ω for the same devices. The VGS-dependent intrinsic channel resistance (RCH) is extracted with different channel lengths for MOSFETs with L = 0.18 μm/0.27 μm/0.36 μm.

Analysis of Instability Mechanism under Simultaneous Positive Gate and Drain Bias Stress in Self-Aligned Top- Gate Amorphous Indium-Zinc-Oxide Thin-Film Transistors

We quantitatively investigated instability mechanisms under simultaneous positive gate and drain bias stress (SPGDBS) in self-aligned top-gate amorphous indium-zinc-oxide thin-film transistors. After SPGDBS (VGS=13 V and VDS=13 V), the parallel shift of the transfer curve into a negative VGS direction and the increase of on current were observed. In order to quantitatively analyze mechanisms of the SPGDBS-induced negative shift of threshold voltage (DVT), we experimentally extracted the density-of-state, and then analyzed by comparing and combining measurement data and TCAD simulation. As results, 19% and 81% of DVT were taken to the donor-state creation and the hole trapping, respectively. This donor-state seems to be doubly ionized oxygen vacancy (VO 2+ ). In addition, it