Surendra S. Rathod

Modeling of threshold voltage, mobility, drain current and subthreshold leakage current in virgin and irradiated silicon-on-insulator fin-shaped field effect transistor device

In this paper, an analytical model for the estimation of threshold voltage shift, mobility, drain current and subthreshold leakage current in virgin as well as irradiated nanoscale fin-shaped field effect transistor (FinFET) device has been presented. The generation of traps in the buried oxide (BOX) and the interface traps at the sidewall influence the characteristics of an irradiated FinFET device. A mobility model considering the influence of quantum mechanical structural confinement and the contribution of interface traps due to all the interfaces is reported in this paper. The modified definition of effective field is adopted to account for nonzero electric field at the back oxide interface of SOI (Silicon-on-Insulator) FinFET device. The results obtained on the basis of our models were compared and contrasted with reported experimental results. A close match was found that validate our analytical modeling approach.

Radiation Effects in MOS-based Devices and Circuits: A Review

Abstract Radiation effects in microelectronic components have been studied for several decades for military and space applications. Understanding radiation effects in electronics is a complex and continually evolving challenge. In this paper, we present an extensive literature review pertaining to the state-of-the-art issues in radiation effects and radiation-hardened circuit design. Various research papers, books and application notes were referred, which take care of various aspects of understanding of radiation effects. In particular, this review gives a bibliographical survey of the current research efforts in the area of radiation effects in metal-oxide-semiconductor based devices and circuits. The paper also presents some of the challenges anticipated in the years to come and enlists further scope for research. A full description of the various methods is beyond the scope of this article; instead, the focus is on providing primary developments that have taken place in the area of radiation effects.

A low-noise, process-variation-tolerant double-gate FinFET based sense amplifier

In this paper, we propose a new independent-gate, process-variation-tolerant double-gate (DG) FinFET based sense amplifier design. The new design exploits the DICE (dual interlock cell) latch and the back gate of a double-gate FinFET (DG FinFET) device for dynamic compensation against process variation. The proposed design improves the sensing delay and show excellent tolerance to process variations as compared to independent-gate sense amplifier (IGSA). The primary advantage of the proposed amplifier over previously reported sense amplifier is the low-noise voltage and large critical charge, making it more stable against single event upsets. Failure probability of the proposed design against process parameter variations is analyzed through Monte Carlo analysis.

Investigation of stack as a low power design technique for 6-T SRAM cell

Low power large scale integration of memory technology is an increasing important and growing area of electronics. In nano-scaled devices, standby power needs to be reduced effectively for high performance System on Chip designs. As per the dasiaInternational Technology of Roadmap for Semiconductors-2007psila, high leakage current in nanometer regime is becoming a significant portion of power dissipation in cmos circuits as threshold voltage, channel length and gate oxide thickness are scaled. This paper explores the possibility of reduction in the energy dissipation in 6T-SRAM cell. This paper evaluates SRAM cell with and without introducing stacking in nanometer regime. Overall leakage in a stack of transistors reduces due to modification of gate to source voltage, threshold voltage and drain induced barrier lowering. T-spice and L-Edit simulation results shows that compared to the conventional high performance SRAM cells, stacked cells offer significant reduction of power consumption. Some of the issue like static noise margin, increase in level of stack and variation in length are discussed in the paper.

DG-FINFET-BASED SRAM CONFIGURATIONS FOR INCREASED SEU IMMUNITY

In this paper, we propose a new circuit level hardening techniques that can decrease the sensitivity of Static Random Access Memory (SRAM) cells to radiation induced Single Event Upsets (SEUs). Five different types of 32 nm double gate (DG)-FinFET-based SRAM cells are analyzed. Proposed SRAM cell outperforms over the unhardened SRAM when exposed to radiation. This is primarily due to the modification of the source potential used to reduce the effect of SEU without affecting normal operation. Static Noise Margin (SNM), Read Noise Margin (RNM), Write Noise Margin (WNM) and Power Delay Product (PDP) are the performance metrics computed for each type of SRAM cell. Effect of back gate voltage and back gate oxide thickness variation on device characteristic show detrimental effects on radiation hardened capabilities of a device. Benchmarking is done against DICE latch and it is found that as compared to DICE latch proposed DG-FinFET SRAM has low transistor count, less area, low recovery time and fault tolerance to internal as well as external nodes.

Comparative Analysis of SEU in FinFET SRAM Cells for Superthreshold and Subthreshold Supply Voltage Operation

Subthreshold circuits are extensively used to reduce power consumption. However, increased susceptibility to radiation particles strikes can significantly impact the reliability of such systems. In this brief, we analyze different FinFET static-random-access-memory (SRAM) cells for single-event-upset immunity and compare their performance when operated with superthreshold and subthreshold supply voltage. Based on these observations, we propose several guidelines for radiation hardening of subthreshold FinFET SRAM designs. These guidelines suggest that the traditional radiation-hardening approaches need to be revisited for subthreshold designs.

Rad-Hard 32 nm FinFET Based Inverters

This paper reports a novel circuit level hardening technique that can decrease sensitivity to radiation induced single event upsets in 32nm FinFET based circuits. Five different types of 32 nm FinFET based inverters are analyzed. Proposed design outperforms over the unhardened circuit when exposed to radiation. This is majorly due to the innovative design technique used to neutralize effect of single event upset without affecting normal operation. Effect of back gate voltage and back gate oxide thickness variation is reported. Results indicate that the proposed design has good hardness to single event upset but has little area and power overheads than the unhardened FinFET based design.

Alpha-particle-induced effects in partially depleted silicon on insulator device: With and without body contact

With the continuous downscaling of CMOS technologies, reliability has become one of the major bottlenecks in the evolution of next generation systems. The radiation-induced soft errors have become one of the most important and challenging failure mechanisms in the modern semi-conductor devices. The authors present an in-depth analysis of alpha-particle-induced effects in deep submicron partially depleted silicon on insulator (PD-SOI) device. Device with body contact as well as device without body contact is analysed. The process and device simulations are done with the latest models. Electrical parameter extraction under different energies of an alpha particle is carried out.

Effect of Border Traps on Electron Mobility of Nano-Scale MOS Devices

It has been recently identified that the near-interfacial oxide trap called ‘border trap’ can strongly affect the radiation response and long term reliability of irradiated MOS devices. But the existing mobility models used to compute radiation induced mobility degradation does not include border traps. Also the quantum mechanical structural confinement plays an important role in the reliability of MOS devices. The aim of this paper is to develop analytical model that accurately predicts mobility of the extremely small silicon thickness MOS devices placed under the radiation. The developed model includes surface roughness, surface mode optical phonon scattering, scattering due to silicon thickness fluctuations and phonon scattering with structural confinements and also the effect of border traps apart from interface and oxide traps. The reported experimental data is extrapolated for the nano-scale devices. From this data, mobility of the irradiated MOSFETs is computed using the developed expression. The results obtained are compared with Sentaurus TCAD simulations and also against numerous reported experimental results. A close match between the developed model, TCAD simulation results and experimental results validate our approach. The study undertaken would help to accurately estimate the radiation induced mobility degradation in MOS devices.