Sudeb Dasgupta

Device and Circuit Co-Design Robustness Studies in the Subthreshold Logic for Ultralow-Power Applications for 32 nm CMOS

Digital circuits operating in a subthreshold region have gained wide interest due to their suitability for applications requiring ultralow power consumption with low-to-medium performance criteria. It has been demonstrated that by appropriately optimizing the devices for subthreshold logic, total energy consumption can be reduced significantly. One of the major concerns for subthreshold circuit design is increased sensitivity to process, voltage, and temperature (PVT) variations. In this paper, we critically study the effect of variations of different device and environmental parameters like gate oxide thickness, channel length, threshold voltage, supply voltage, temperature, and reverse body bias on subthreshold circuit performance for 32 nm bulk CMOS. From the study, we conclude that alternative devices like double-gate silicon-on-insulator (DGSOI) are better candidates in terms of performance, robustness and PVT insensitivity as compared to bulk circuits for both static CMOS and pseudo NMOS logic families. We also study the performance and robustness comparisons of bulk CMOS and DGSOI subthreshold basic logic gates with and without parameter variations and we observe 60-70% improvement in power delay product and roughly 50% better tolerance to PVT variations of DGSOI subthreshold logic circuits compared to bulk CMOS subthreshold circuits at the 32 nm node.

High-Performance and Robust SRAM Cell Based on Asymmetric Dual-

This paper proposes a new asymmetric underlap Fin-Field Effect Transistor (FinFET) structure using a dual- k spacer. Asymmetric dual-spacer at source shows excellent gate control over the channel due to increase in the outer fringe field at gate/source underlap. Hence, this structure exhibits a superior short-channel effect metric over the conventional/single-spacer underlap FinFET. The proposed asymmetric structure enhances static random access memories (SRAMs) performance in terms of robustness, access times as well as leakage power during the hold, read, and write operations. The hold static noise margin and write margin increases by 5.16% and 5.66%, respectively. The read stability enhances by 13.75% and 19.35% over conventional FinFET SRAM circuit. Furthermore, the leakage power reduces by 60%, and write access time improves by 23.63%. Compared with conventional FinFET-based SRAM, same bit-cell area and read delay are associated with the proposed structure. Supply voltage scalability on SRAM design metrics is also investigated. In addition to SRAM application, underlap length, lateral source/drain doping gradient, and the high- k spacer width are optimized for high-performance digital applications.

k

In this paper the analysis of SNM, RNM, WNM and static power variation with width of access, load and driver have been carried out for nanoscale FinFET based SRAM cell. FinFET based SRAM design has been proposed as an alternative solution to the bulk devices. It can be inferred from the results that with increase in the width of driver FinFET, the high SNM reduces and low SNM increases. This is due the fact that the leakage current is considerably reduced due to increased control of the FinFET device structure, resulting relatively in highIon/Ioffratio. Further, the effect of process variation on the SRAM cell performance was analyzed using Monte Carlo simulation on HSPICE. The Monte Carlo simulation results for RNM and WNM to quantify the effect of process variation arising due to variation in FinFETs widths. The simulation was carried out for 1000 values, assuming 3σ equal to 10% of the mean value. Two structures of the FinFET viz. the standard PTM model and an underlapped FinFET have been also used for the simulations. It was identified that while the relative levels of the noise margins were lower for the underlapped case, the standard deviation was considerably lower too. In this work we also analyze the effect of temperature on noise margins and static power for FinFET based SRAM cell. FinFET is suitable for future nanoscale memory circuits design due to its reduced Short Channel Effects (SCE) and leakage current.

Spacer FinFETs

In recent years, subthreshold operation has gained a lot of attention due to ultra low-power consumption in applications requiring low to medium performance. It has also been shown that by optimizing the device structure, power consumption of digital subthreshold logic can be further minimized while improving its performance. Therefore, subthreshold circuit design is very promising for future ultra low-energy sensor applications as well as high-performance parallel processing. This paper deals with various device and circuit design challenges associated with the state of the art in optimal digital subthreshold circuit design and reviews device design methodologies and circuit topologies for optimal digital subthreshold operation. This paper identifies the suitable candidates for subthreshold operation at device and circuit levels for optimal subthreshold circuit design and provides an effective roadmap for digital designers interested to work with ultra low-power applications.

Nanoscale FinFET Based SRAM Cell Design: Analysis of Performance Metric, Process Variation, Underlapped FinFET, and Temperature Effect

Among the multigate structures, FinFET is emerging as a promising candidate due to its better gate electrostatic control and ease of manufacturability. However, loss of gate electrostatic integrity (EI) is still observed in FinFET while it is scaled down to nano-scale regime, resulting in deterioration of analog performance. Most importantly, precise dimensional requirements and process challenges are major hurdles at nano-scale regime resulting in device-to-device variability. Nevertheless, efficient use of gate sidewall fringing fields, by use of an inner high-k spacer, can restore the loss of gate control. In this paper, we observe that, due to excellent gate EI, the analog performance of dual-k spacer-based underlap N/P-FinFET is better than the conventional low-k N/P-FinFET. Simulation results at 12 nm gate length reveal that dual-k N/P-FinFETs are capable of targeting high-gain, low-power, and moderate frequency of operation even with lower aspect ratio (fin height/fin width) and higher fin width, oxide thickness, and lateral straggle. In addition, the figures of merit of dual-k N/P-FinFETs are less variable to major parametric variations such as fin width and oxide thickness. These attractive features prove to be handy in designing circuitry for low-power battery-operated portable gadgets.

Device and circuit design challenges in the digital subthreshold region for ultralow-power applications

During recent years, high-k spacer materials have been extensively studied for the enhancement of electrostatic control and suppression of short-channel effects in nanoscaled devices. However, the exorbitant increase in fringe capacitance due to high-k spacers deteriorates the dynamic circuit performance that restricts researchers using these devices in high-performance circuits. For the first time, this paper demonstrates the usage of high-k spacer material with an optimized length for effective reduction of circuit delay and an improvement in robustness. An improvised symmetric dual-k spacer (SymD-k) underlap trigate FinFET architecture termed as SymD-k is employed for this purpose. From extensive 3-D simulations, this paper demonstrates that SymD-k device significantly improves overall circuit delay and robustness (noise-margins) with fully capturing the fringe capacitance effects. A CMOS inverter and a three-stage ring-oscillator (RO3) are adopted to carefully investigate the performances. In comparison with the conventional device, the SymD-k device speeds up the RO3 circuit by 27% and 33% using high-k spacer dielectric HfO2 and TiO2, respectively. However, a purely high-k FinFET device deteriorates the RO3 delay per stage up to 11%. Furthermore, the effect of underlap length and supply voltage on SymD-k-based RO3 delay over the conventional ones are also dealt in.

Design and Analysis of Analog Performance of Dual-k Spacer Underlap N/P-FinFET at 12 nm Gate Length

As the MOSFET is scaled into a nanoscale regime, spreading of source/drain (S/D) dopant into the channel region will facilitate the lateral electric field spread into the channel and in turn deteriorate the gate electrostatic integrity. The short channel effects and performance are aggravated with the increase in lateral straggle (σ_L) of S/D Gaussian profile. In this paper, we have developed an analytical potential model that includes the effect of σ_L. Subsequently, an expression for threshold voltage and linear/saturation region drain current is proposed and the effect of σ_L over the transconductance (g_m), output conductance (g_ds), and intrinsic gain (A_V0) is studied.

Investigation of Symmetric Dual-k Spacer Trigate FinFETs From Delay Perspective

Novel analytical models for subthreshold current and subthreshold slope of a generic underlap DGMOSFET are proposed. The proposed models are validated with published models, experimental data along with numerical simulation results. The reasonably good agreement shows the accuracy of the proposed model. It is demonstrated how device subthreshold leakage current and subthreshold slope values can be favorably affected by proper back gate biasing, back gate asymmetry and gate work function engineering in combination with gate underlap engineering. It is demonstrated that independent gate operation in combination with gate underlap engineering significantly reduce subthreshold leakage currents as compared to nonunderlap-tied gate DGMOSFET. With the reduction in body thickness, an improvement in subthreshold slope value of underlap 4T DGMOSFET is seen, particularly as back/front gate oxide asymmetry. Developed models demonstrate that asymmetric work function underlap 4T DGMOSFETs would have better device subthreshold slope value along with increased back gate oxide asymmetry.

Analytical Modeling of a Double Gate MOSFET Considering Source/Drain Lateral Gaussian Doping Profile

Multigate structures have better short channel control than conventional bulk devices due to increased gate electrostatic control. FinFET is a promising candidate among multigate structures due to its ease of manufacturability. The RF performance of FinFET is affected by gate controlled parameters such as transconductance, output conductance and total gate capacitance. In this paper we have used dual-k spacers in underlap FinFETs to improve the gate electrostatic integrity. The inner high-k spacer helps in better screening out the gate sidewall fringing fields, thereby, increasing transconductance and reducing output conductance with increase in total gate capacitance. At 16nm gate lengths, we have observed that, the intrinsic gain of dual-k spacer based FinFET can be increased by more than 100% (>6dB) without affecting cutoff frequency and maximum oscillation frequency, as compared to conventional single spacer based FinFET. Improvement in cutoff frequency by 11% and maximum oscillation frequency by 5% can be achieved, when the gate lengths are scaled down to 12nm, in addition to 2.75 times (8.8dB) increase in intrinsic gain.

Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied-independent gate and symmetric-asymmetric options

Double gate FinFETs are shown to be better candidates for subthreshold logic design than equivalent bulk devices. However it is not so clear which configuration of DG FinFETs will be more optimal for subthreshold logic. In this paper, we compare the different device and circuit level performance metrics of DG FinFETs with symmetric, asymmetric, tied and independent gate options for subthreshold logic. We observe that energy delay product (EDP) shows a better subthreshold performance metric than power delay product (PDP) and it is observed that the tied gate symmetric option has ~78% lower EDP value than that of independent gate option for subthreshold logic. The asymmetry in back gate oxide thickness adds to further reduction in EDP for tied gate and has no significant effect on independent gate option. The robustness (measured in terms of % variation in device/circuit performance metrics for a +/-10% variation in design parameters) of DG FinFETs with various options has also been investigated in presence of different design parameter variations such as silicon body thickness, channel length, threshold voltage, supply voltage and temperature, etc. Independent gate option has been seen to be more robust (~40% less) than that of tied gate option for subthreshold logic. Comparison of logic families for subthreshold regime with DG FinFET options shows that for tied gate option, sub-CMOS, sub-Domino and sub-DCVSL have almost similar and better energy consumption and robustness characteristics with respect to PVT variations than other families.