Suriyaprakash Natarajan

Case Study on Speed Failure Causes in a Microprocessor

In this article, we identify the underlying speed paths and perform a detailed analysis on the effects of multiple input switching, cross-coupling noise, and localized voltage drop on microprocessor. We employ cycle-wise clock shrinks on a tester combined with a CAD methodology to unintrusively identify and analyze these speed paths. Understanding the causes of speed failures can help designers make better power and performance tradeoffs.

Selecting High-Quality Delay Tests for Manufacturing Test and Debug

The process of debugging timing failures requires the selection of a small set of high-quality tests which can excite critical paths and cause a circuit to fail at as low a frequency as possible. Since the primary source of such vectors are functional vectors which can run into millions of cycles, a cost-effective methodology for selecting high quality delay tests should not require an excessive computational effort and should guarantee reasonable accuracy. We propose two metrics for estimating the delay under a given test to aid in ranking tests in order of their ability to excite critical delays. The first metric is path-based, i.e., it estimates delays of excited paths, and associates the worst-case delay over all the excited paths with the test. The second metric is cone-based, i.e., it estimates the worst-case delay for the logic cone of every output without considering paths explicitly, and associates the largest delay over all the cones with the test. For each of these two metrics, we evaluate the correlation between the metric and the delay computed by circuit simulation. Results on combinational benchmark circuits demonstrate that the metrics achieve reasonable accuracy in test selection at a significantly lower computation time than circuit simulation

Path delay fault simulation on large industrial designs

Path delay fault simulation performance on multi-cycle delay paths common in industrial designs is discussed using paths from a large block in a microprocessor and a functional test vector suite. We profile fault simulation performance using a novel multi-cycle path delay fault simulator. Our experiments show that path delay fault simulation run-time grows linearly with path list size. Contrary to commonly held notion that path delay fault simulation is more expensive than stuck-at fault simulation, our experiments show that performance of path delay fault grading is comparable to that of stuck-at fault grading. Finally, we propose and evaluate a heuristic that can improve path delay fault simulation performance and also aid in selection of tests for speed-limiting paths.

Scalable and efficient analog parametric fault identification

Analog circuits embedded in large mixed-signal designs can fail due to unexpected process parameter excursions. To evaluate manufacturing tests in terms of their ability to detect such failures, parametric faults leading to circuit failures should be identified. This paper proposes an iterative sampling method to identify these faults in large-scale analog circuits with a constrained simulation budget. Experiment results on two circuits from a serial IO interface demonstrate the effectiveness of the methodology. The proposed method identifies a significantly larger and diverse set of critical parametric faults compared to a Monte Carlo-based approach for identical computational budget, particularly for cases involving significant process variations.

Path coverage based functional test generation for processor marginality validation

Functional test content to screen for electrical marginalities during silicon validation are not generated with the goal of identifying speed-limiting paths, adversely affecting the quality and efficiency of validation. We propose a methodology to generate functional tests to excite pre-silicon timing-critical paths along with environmental effects such as voltage droop. These tests are to replace random/function-targeted content as the source for identifying speed failures during silicon validation. The effectiveness of this methodology is demonstrated through silicon experiments on a recent processor.

On efficient generation of instruction sequences to test for delay defects in a processor

We present a technique that deals with the problem of efficiently generating instruction sequences to test for delay defects in a processor. These instruction sequences are loaded into the cache of a processor and the processor is run in its normal functional (native) mode to test itself. The methodology that we present avoids the significant increase in search space of a previous method while generating tests. We also present a technique which increases the probability of detecting multiple delay faults with a single instruction sequence. This technique can help immensely in reducing the cost of test. We demonstrate the effectiveness of our technique on an off-the shelf processor.

Analysis of Defects and Variations in Embedded Spin Transfer Torque (STT) MRAM Arrays

Spin transfer torque magnetic random access memory (STT-MRAM) is a competitive, future memory technology for last-level embedded caches. It exhibits ultra-high density (3-4X of SRAM), non-volatility, nano-second Read and Write speeds, and process and voltage compatibility with CMOS. As the design and fabrication process mature for the STT-MRAM, there is a need to study the various fault models that can affect this novel memory technology. This work presents a comprehensive analysis of fault models which represent both parametric variations as well as defects (opens and shorts) in STT MRAM. Sensitivity of Read, Write and Retention to process (material and lithographic) parameters, defects (both intra-cell and inter-cell) and data patterns are studied.

Framework for analog test coverage

Measurement of the quality of tests run during high volume manufacturing of microprocessors is important to ensure desired outgoing product quality. For digital logic on die, such measurement is performed using techniques such as fast event-driven fault simulation using mature fault models such as stuck-at and transition faults. For analog modules on die, such test quality measurement is not performed in practice due to lack of (a) mature fault models to describe analog failures, and (b) automated, efficient and accurate fault simulation methods. This work is a first step towards our objective of establishing a practical methodology to measure analog test quality. We show promising results of a semi-automated fault simulation approach on analog modules of a high speed serial IO receiver that compares (a) two manufacturing tests in terms of their defect detection capability as measured by their fault coverages for gross and parametric faults, and, (b) the accuracy and performance of using models versus schematics for fault effect propagation.

Fast eye diagram analysis for high-speed CMOS circuits

We present an efficient technique for analyzing eye diagrams of high speed CMOS circuits in the presence of non-idealities like noise and jitter. Our method involves geometric manipulations of the eye diagram topology to find area within the eye contours. We introduce random tree based simulations as an approach to computing the desired area. We typically show 20× speedup in generating the eye diagram as compared to the state-of-the-art Monte Carlo simulation based eye diagram analysis. For the same number of samples, Monte Carlo produces an eye diagram that is 8.51% smaller than the ideal eye diagram. We generate an eye diagram that is 53.52% smaller than the ideal eye, showing a 47% improvement in quality.

A Model Study of Defects and Faults in Embedded Spin Transfer Torque (STT) MRAM Arrays

There has been a significant interest in Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) as a candidate for emerging memory technology for last-level embedded caches in the recent years. High density (3-4x of SRAM), non-volatility, nano-second Read and Write speeds, and process and voltage compatibility with CMOS are the attractive properties of this technology. A few studies have expounded on the reliability in this technology but various fault manifestations have not been studied in detail in the past. This paper attempts to study the fault models in STT-MRAM under both parametric variations as well as electrical defects (opens and shorts). Sensitivity of Read, Write and Retention to material and lithographic process parameters has been studied. Also electrical defects viz. intra-cell and inter-cell opens and shorts have been considered and the corresponding fault models have been identified and classified.